diff --git a/VERSION b/VERSION
index 61ce01b..850e742 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-1.13.2
+1.14.0
diff --git a/internal/common/omci/onu_mib_db.go b/internal/common/omci/onu_mib_db.go
index eddc8dc..0fad947 100644
--- a/internal/common/omci/onu_mib_db.go
+++ b/internal/common/omci/onu_mib_db.go
@@ -96,7 +96,7 @@
 	tcontSlotId       byte = 0x80 // why is this not the same as the cardHolderSlotID, it does not point to anything
 	aniGId            byte = 0x01
 
-	upstreamPriorityQueues   = 8  // Number of queues for each T-CONT
+	upstreamPriorityQueues   = 16 // Number of queues for each T-CONT
 	downstreamPriorityQueues = 16 // Number of queues for each PPTP
 	tconts                   = 8  // NOTE will we ever need to configure this?
 	// trafficSchedulers        = 8  // NOTE will we ever need to configure this?
diff --git a/internal/common/omci/onu_mib_db_test.go b/internal/common/omci/onu_mib_db_test.go
index 75bcf7d..c20fdfc 100644
--- a/internal/common/omci/onu_mib_db_test.go
+++ b/internal/common/omci/onu_mib_db_test.go
@@ -67,13 +67,13 @@
 	const uniPortCount = 4
 	mibDb, err := GenerateMibDatabase(uniPortCount, 0, common.XGSPON)
 
-	expectedItems := 9                     //ONU-G + 2 Circuit Packs (4 messages each)
-	expectedItems += 2 * uniPortCount      // 1 PPTP and 1 UniG per UNI
-	expectedItems += 1                     // ANI-G
-	expectedItems += 2 * tconts            // T-CONT and traffic schedulers
-	expectedItems += 1                     // ONU-2g
-	expectedItems += 2 * 8 * tconts        // 8 upstream queues for each T-CONT, and we report each queue twice
-	expectedItems += 2 * 16 * uniPortCount // 16 downstream queues for each T-CONT, and we report each queue twice
+	expectedItems := 9                                           //ONU-G + 2 Circuit Packs (4 messages each)
+	expectedItems += 2 * uniPortCount                            // 1 PPTP and 1 UniG per UNI
+	expectedItems += 1                                           // ANI-G
+	expectedItems += 2 * tconts                                  // T-CONT and traffic schedulers
+	expectedItems += 1                                           // ONU-2g
+	expectedItems += 2 * upstreamPriorityQueues * tconts         // upstream queues for each T-CONT, and we report each queue twice
+	expectedItems += 2 * downstreamPriorityQueues * uniPortCount // downstream queues for each T-CONT, and we report each queue twice
 
 	assert.NoError(t, err)
 	assert.NotNil(t, mibDb)
@@ -110,13 +110,13 @@
 	const potsPortCount = 1
 	mibDb, err := GenerateMibDatabase(uniPortCount, potsPortCount, common.XGSPON)
 
-	expectedItems := 13                                      //ONU-G + 3 Circuit Packs (4 messages each)
-	expectedItems += 2 * (uniPortCount + potsPortCount)      // 1 PPTP and 1 UniG per UNI
-	expectedItems += 1                                       // ANI-G
-	expectedItems += 2 * tconts                              // T-CONT and traffic schedulers
-	expectedItems += 1                                       // ONU-2g
-	expectedItems += 2 * 8 * tconts                          // 8 upstream queues for each T-CONT, and we report each queue twice
-	expectedItems += 2 * 16 * (uniPortCount + potsPortCount) // 16 downstream queues for each T-CONT, and we report each queue twice
+	expectedItems := 13                                                            //ONU-G + 3 Circuit Packs (4 messages each)
+	expectedItems += 2 * (uniPortCount + potsPortCount)                            // 1 PPTP and 1 UniG per UNI
+	expectedItems += 1                                                             // ANI-G
+	expectedItems += 2 * tconts                                                    // T-CONT and traffic schedulers
+	expectedItems += 1                                                             // ONU-2g
+	expectedItems += 2 * upstreamPriorityQueues * tconts                           // upstream queues for each T-CONT, and we report each queue twice
+	expectedItems += 2 * downstreamPriorityQueues * (uniPortCount + potsPortCount) // downstream queues for each T-CONT, and we report each queue twice
 
 	assert.NoError(t, err)
 	assert.NotNil(t, mibDb)
@@ -152,7 +152,7 @@
 	}
 
 	const uniPortCount = 4
-	const baseMibEntries = 291                    // see Test_GenerateMibDatabase for breakdown
+	const baseMibEntries = 419                    // see Test_GenerateMibDatabase for breakdown
 	const expectedMibEntries = baseMibEntries + 1 // expecting one hardcoded packet
 	mibDb, err := GenerateMibDatabase(uniPortCount, 0, common.XGSPON)