commit c948d0bf6d2d789da1f0c2098e90497e33c5a90a
author Dan Talayco <dan.talayco@bigswitch.com> Fri Mar 23 12:17:54 2012 -0700
committer Dan Talayco <dan.talayco@bigswitch.com> Fri Mar 23 12:17:54 2012 -0700
tree 7fdf9ab1bf86861f9fb2dc74fd2379281a14aeee
parent cfa172f4af6efbd3a76be423a9f300b8a773ad40

Added L2 dest addr and send to ingress port

Some small infra changes to support this

tests/pktact.py

diff --git a/tests/pktact.py b/tests/pktact.py
index 0bd21dc..11f267b 100644
--- a/tests/pktact.py
+++ b/tests/pktact.py
@@ -970,6 +970,22 @@
         flow_match_test(self, pa_port_map, pkt=pkt, exp_pkt=exp_pkt, 
                         action_list=acts, max_test=2, egr_count=-1)
 
+class ModifyL2DstIngress(BaseMatchCase):
+    """
+    Modify the L2 dest and send to the ingress port
+    """
+    def runTest(self):
+        sup_acts = supported_actions_get(self)
+        if not (sup_acts & 1 << ofp.OFPAT_SET_DL_DST):
+            skip_message_emit(self, "ModifyL2dstMC test")
+            return
+
+        (pkt, exp_pkt, acts) = pkt_action_setup(self, mod_fields=['dl_dst'],
+                                                check_test_params=True)
+        flow_match_test(self, pa_port_map, pkt=pkt, exp_pkt=exp_pkt, 
+                        action_list=acts, max_test=2, egr_count=0,
+                        ing_port=True)
+
 class ModifyL2SrcMC(BaseMatchCase):
     """
     Modify the source MAC address (TP1) and send to multiple

tests/testutils.py

diff --git a/tests/testutils.py b/tests/testutils.py
index fe705f4..a5214af 100644
--- a/tests/testutils.py
+++ b/tests/testutils.py
@@ -246,7 +246,7 @@
                              "Unexpected pkt on port " + str(ofport))
 
 
-def receive_pkt_verify(parent, egr_ports, exp_pkt):
+def receive_pkt_verify(parent, egr_ports, exp_pkt, ing_port):
     """
     Receive a packet and verify it matches an expected value
     @param egr_port A single port or list of ports
@@ -264,6 +264,8 @@
 
     # Expect a packet from each port on egr port list
     for egr_port in egr_port_list:
+        if egr_port == ofp.OFPP_IN_PORT:
+            egr_port = ing_port
         (rcv_port, rcv_pkt, pkt_time) = parent.dataplane.poll(
             port_number=egr_port, timeout=1, exp_pkt=exp_pkt_arg)
 
@@ -490,7 +492,7 @@
 
     if exp_pkt is None:
         exp_pkt = pkt
-    receive_pkt_verify(parent, egr_ports, exp_pkt)
+    receive_pkt_verify(parent, egr_ports, exp_pkt, ing_port)
 
     if check_expire:
         #@todo Not all HW supports both pkt and byte counters
@@ -506,6 +508,9 @@
     @returns An empty list if unable to find enough ports
     """
 
+    if how_many == 0:
+        return []
+
     count = 0
     egr_ports = []
     for egr_idx in range(len(of_ports)): 
@@ -519,7 +524,7 @@
     
 def flow_match_test(parent, port_map, wildcards=0, dl_vlan=-1, pkt=None, 
                     exp_pkt=None, action_list=None, check_expire=False, 
-                    max_test=0, egr_count=1):
+                    max_test=0, egr_count=1, ing_port=False):
     """
     Run flow_match_test_port_pair on all port pairs
 
@@ -546,6 +551,8 @@
         ingress_port = of_ports[ing_idx]
         egr_ports = get_egr_list(parent, of_ports, egr_count, 
                                  exclude_list=[ingress_port])
+        if ing_port:
+            egr_ports.append(ofp.OFPP_IN_PORT)
         if len(egr_ports) == 0:
             parent.assertTrue(0, "Failed to generate egress port list")