commit d2e93aa1cc8366e43a5115631ca307c99e11f356
author Rich Lane <rich.lane@bigswitch.com> Wed Dec 05 17:55:46 2012 -0800
committer Rich Lane <rich.lane@bigswitch.com> Thu Dec 06 17:02:48 2012 -0800
tree a0af3a507c495151872215863fff7e6aa7a2e2c5
parent b5c7379adf9f909d2f50c2481f523e5d39cf3617

dataplane: record wall clock time when receiving packet

time.clock() returns processor time which is not useful.

platforms/ovs-dummy.py

diff --git a/platforms/ovs-dummy.py b/platforms/ovs-dummy.py
index bc6f862..2dad1a5 100644
--- a/platforms/ovs-dummy.py
+++ b/platforms/ovs-dummy.py
@@ -108,7 +108,7 @@
                 data = self.socket.recv(n)
                 rxbuf += data
                 if len(data) == n and len(rxbuf) > 2:
-                    rcvtime = time.clock()
+                    rcvtime = time.time()
                     self.logger.debug("Pkt len " + str(len(rxbuf)) +
                              " in at " + str(rcvtime) + " on port " +
                              str(self.port_number))