BAL and Maple Release 2.2
Signed-off-by: Shad Ansari <developer@Carbon.local>
diff --git a/bcm68620_release/release/host_customized/pcie/Makefile b/bcm68620_release/release/host_customized/pcie/Makefile
new file mode 100755
index 0000000..338d3cc
--- /dev/null
+++ b/bcm68620_release/release/host_customized/pcie/Makefile
@@ -0,0 +1,24 @@
+# PCIE driver
+# host specific
+#
+MOD_NAME = pcie_mod
+MOD_DEPS = pcie
+
+MOD_SUPPRESS_OS_DEP = y
+
+ifeq ("$(OS_KERNEL)", "linux")
+ MOD_TYPE = linux_lib
+ srcs = bcmolt_tr_pcie_specific.c
+else
+ MOD_TYPE = lib
+endif
+
+# If called by linux kernel builder - add include paths manually.
+# It is not elegant, but we'll not have many linux modules
+ifneq ("$(KBUILD_SRC)", "")
+ -include $(OUT_DIR_BASE)/Makefile.config.$(MOD_NAME)
+endif
+
+USE_LINT = yes
+
+
diff --git a/bcm68620_release/release/host_customized/pcie/bcmolt_tr_pcie_specific.c b/bcm68620_release/release/host_customized/pcie/bcmolt_tr_pcie_specific.c
new file mode 100755
index 0000000..94102bc
--- /dev/null
+++ b/bcm68620_release/release/host_customized/pcie/bcmolt_tr_pcie_specific.c
@@ -0,0 +1,106 @@
+/*
+<:copyright-BRCM:2016:DUAL/GPL:standard
+
+ Broadcom Proprietary and Confidential.(c) 2016 Broadcom
+ All Rights Reserved
+
+Unless you and Broadcom execute a separate written software license
+agreement governing use of this software, this software is licensed
+to you under the terms of the GNU General Public License version 2
+(the "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php,
+with the following added to such license:
+
+ As a special exception, the copyright holders of this software give
+ you permission to link this software with independent modules, and
+ to copy and distribute the resulting executable under terms of your
+ choice, provided that you also meet, for each linked independent
+ module, the terms and conditions of the license of that module.
+ An independent module is a module which is not derived from this
+ software. The special exception does not apply to any modifications
+ of the software.
+
+Not withstanding the above, under no circumstances may you combine
+this software in any way with any other Broadcom software provided
+under a license other than the GPL, without Broadcom's express prior
+written consent.
+
+:>
+ */
+
+#include "bcmos_system.h"
+#include "bcmtr_pcie.h"
+#include "bcmolt_tr_pcie_specific.h"
+
+extern f_bcmtr_int bcmtr_pcie_rx_irq_handler;
+extern f_bcmtr_int bcmtr_pcie_tx_irq_handler;
+static bcmos_fastlock isr_lock;
+
+/***************************************************************/
+/* need to pass thru all the devices - check if irq is SHARED */
+/***************************************************************/
+static int bcmtr_rx_isr(int irq, void *isr_info)
+{
+ uint32_t isr_reg;
+ uint32_t mask_reg;
+ long flags;
+ int handled = 0;
+ bcm_pcied_isr_data *isr_data = (bcm_pcied_isr_data *)isr_info;
+
+ flags = bcmos_fastlock_lock(&isr_lock);
+
+ isr_reg = bcm_pci_read32((uint32_t*)(isr_data->pcie_reg_base + DMA_INTR_STATUS));
+ mask_reg = ~bcm_pci_read32((uint32_t*)(isr_data->pcie_reg_base + DMA_INTR_MASK_STATUS));
+
+ if ((isr_reg & mask_reg)& DMA_TX_DONE_MASK)
+ {
+ /* handle TX DONE interrupt */
+ isr_data->tx_done_num++;
+
+ if (bcmtr_pcie_tx_irq_handler)
+ bcmtr_pcie_tx_irq_handler(isr_data->device);
+
+ handled = 1;
+ }
+
+ if ((isr_reg & mask_reg ) & DMA_RX_DONE_MASK)
+ {
+ /* handle RX DONE interrupt */
+ isr_data->rx_done_num++;
+
+ if (bcmtr_pcie_rx_irq_handler)
+ bcmtr_pcie_rx_irq_handler(isr_data->device);
+
+ handled = 1;
+ }
+
+ if (isr_reg & (DMA_RX_ERROR_MASK | DMA_TX_ERROR_MASK))
+ {
+ if (isr_reg & DMA_RX_ERROR_MASK)
+ isr_data->rx_err_num++;
+ if (isr_reg & DMA_TX_ERROR_MASK)
+ isr_data->tx_err_num++;
+ /* clear interrupt error interrupt */
+ bcm_pci_write32((uint32_t*)(isr_data->pcie_reg_base + DMA_INTR_CLEAR), DMA_RX_ERROR_MASK | DMA_TX_ERROR_MASK);
+ handled = 1;
+ }
+
+ bcmos_fastlock_unlock(&isr_lock, flags);
+
+ return handled;
+}
+
+void bcmtr_connect_isr(void *isr_info)
+{
+ uint32_t flags = 0;
+
+ bcm_pcied_isr_data *isr_data = (bcm_pcied_isr_data *)isr_info;
+ bcmos_fastlock_init(&isr_lock, flags);
+ /* connect interrupt to system cpu - 0 */
+ bcmos_int_connect((int)isr_data->rx_irq, 0, BCMOS_IRQ_SHARED, bcmtr_rx_isr, "dmaisr", isr_data);
+}
+
+#ifdef __KERNEL__
+EXPORT_SYMBOL(bcmtr_connect_isr);
+#endif
+
+
diff --git a/bcm68620_release/release/host_customized/pcie/bcmolt_tr_pcie_specific.h b/bcm68620_release/release/host_customized/pcie/bcmolt_tr_pcie_specific.h
new file mode 100644
index 0000000..c8c8ac1
--- /dev/null
+++ b/bcm68620_release/release/host_customized/pcie/bcmolt_tr_pcie_specific.h
@@ -0,0 +1,113 @@
+/*
+<:copyright-BRCM:2016:DUAL/GPL:standard
+
+ Broadcom Proprietary and Confidential.(c) 2016 Broadcom
+ All Rights Reserved
+
+Unless you and Broadcom execute a separate written software license
+agreement governing use of this software, this software is licensed
+to you under the terms of the GNU General Public License version 2
+(the "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php,
+with the following added to such license:
+
+ As a special exception, the copyright holders of this software give
+ you permission to link this software with independent modules, and
+ to copy and distribute the resulting executable under terms of your
+ choice, provided that you also meet, for each linked independent
+ module, the terms and conditions of the license of that module.
+ An independent module is a module which is not derived from this
+ software. The special exception does not apply to any modifications
+ of the software.
+
+Not withstanding the above, under no circumstances may you combine
+this software in any way with any other Broadcom software provided
+under a license other than the GPL, without Broadcom's express prior
+written consent.
+
+:>
+ */
+
+#ifndef BCMOLT_TR_PCIE_SPECIFIC_H_
+#define BCMOLT_TR_PCIE_SPECIFIC_H_
+
+#include "bcmos_system.h"
+#include "bcmtr_pcie.h"
+
+#define DESCRIPTOR_CONTROL 0x00064410 /* Tx Software Descriptor List Control and Status */
+#define WAKEUP_DMA 0x00064414 /* Tx Wake Control */
+#define ERROR_STATUS 0x00064418 /* Tx Engine Error Status */
+
+#define INTR2_PCI_STATUS 0x00064318 /* PCI interrupt Status Register */
+
+#define DMA_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK 0x00000001
+#define DMA_TX_WAKE_CTRL_WAKE_MASK 0x00000001
+
+#define DMA_INTR_STATUS 0x00064318 /* PCI interrupt Status Register */
+#define DMA_INTR_CLEAR 0x00064320 /* PCI interrupt Clear Register */
+#define DMA_INTR_MASK_SET 0x00064328 /* PCI interrupt Mask Set Register */
+#define DMA_INTR_MASK_CLEAR 0x0006432c /* PCI interrupt Mask Clear Register */
+#define DMA_INTR_MASK_STATUS 0x00064324 /* PCI interrupt Mask & Status Register */
+
+#define DMA_RX_ERROR_MASK 0x00000008
+#define DMA_RX_DONE_MASK 0x00000004
+#define DMA_TX_DONE_MASK 0x00000001
+#define DMA_TX_ERROR_MASK 0x00000002
+
+#define PCIE_L2_INTR_MASK 0x00000020 /* L2 interrupt bit in L1 interrupt status */
+
+#define DMA_INTR1_STATUS 0x00069300 /* Interrupt Status Register */
+#define DMA_INTR1_MASK_CLEAR 0x0006930c /* Interrupt Mask Clear Register */
+#define DMA_INTR1_MASK_SET 0x00069308 /* Interrupt Mask Set Register */
+#define DMA_INTA_MASK 0x00000002
+#define DMA_INTA_SHIFT 1
+#define PCIE_STATUS_OFFSET 0x00064068 /* PCIE_PCIE_PCIE_0_PCIE_PCIE_0_MISC_PCIE_STATUS */
+
+void bcmtr_connect_isr(void *isr_info);
+
+/* first parameter is the dest PD, the second parameter is the source field */
+static inline void bcmtr_set_dest_buffer_address(uint32_t *pd, void *value)
+{
+ uint64_t tmp = bcmos_virt_to_phys(value);
+
+ bcm_pci_write32(&pd[PCI_PACKET_LOW_INDEX], (uint32_t)( tmp & 0xffffffffUL));
+ bcm_pci_write32(&pd[PCI_PACKET_HIGH_INDEX], (uint32_t)((tmp >> 32) & 0xffffffffUL));
+}
+
+/* first parameter is the dest PD, the second parameter is the source field */
+static inline void bcmtr_set_source_buffer_address(uint32_t *pd, void *value)
+{
+ uint64_t tmp = bcmos_virt_to_phys(value);
+
+ bcm_pci_write32(&pd[PCI_PACKET_LOW_INDEX], (uint32_t)( tmp & 0xffffffffUL));
+ bcm_pci_write32(&pd[PCI_PACKET_HIGH_INDEX], (uint32_t)((tmp >> 32) & 0xffffffffUL));
+}
+
+static inline bcmos_errno bcmtr_create_tu_rings(uint32_t txlength, uint32_t rxlength,
+ void **txptr, void **rxptr,
+ void **txptr_orig, void **rxptr_orig,
+ unsigned long pcie_reg_base)
+{
+ *txptr = NULL;
+ *rxptr_orig = NULL;
+ *txptr = NULL;
+ *rxptr_orig = NULL;
+
+ return BCM_ERR_OK;
+}
+static inline void bcmtr_pcie_specific_init(unsigned long pcie_reg_base) {}
+static inline void bcmtr_pcie_free_rings(uint32_t device, uint32_t *tx_ptr, uint32_t * rx_ptr){}
+static inline void bcmtr_pcie_free_irq(uint32_t irq, void *priv)
+{
+#ifndef SIMULATION_BUILD
+ bcmos_int_disconnect((int)irq, priv);
+#endif
+}
+
+#define TX_LOCKDEF bcmos_mutex tx_lock;
+#define CREATE_TXLOCK(i) bcmos_mutex_create(&bcmtr_pcie_data[i].tx_lock, 0, NULL)
+#define DESTROY_TXLOCK(i) bcmos_mutex_destroy(&bcmtr_pcie_data[i].tx_lock)
+#define LOCK_TX() bcmos_mutex_lock(¤t_device->tx_lock)
+#define UNLOCK_TX() bcmos_mutex_unlock(¤t_device->tx_lock)
+
+#endif
+