diff --git a/bcm68620_release/release/host_driver/fld/Makefile b/bcm68620_release/release/host_driver/fld/Makefile
new file mode 100644
index 0000000..b4571ca
--- /dev/null
+++ b/bcm68620_release/release/host_driver/fld/Makefile
@@ -0,0 +1,38 @@
+# FLD driver
+# - low-level FLD driver (load functions)
+#
+MOD_NAME = fld
+MOD_DEPS = model
+
+ifneq ("$(RELEASE_BUILD)", "y")
+    MOD_INC_DIRS = $(SRC_DIR) common/drivers/$(PLATFORM)/fld
+endif
+
+ifeq ("$(ENABLE_TRACE)", "y")
+	MOD_DEFS += -DTX_ENABLE_EVENT_TRACE
+    ifeq ("$(DEBUG_TRACE_INIT)", "y")
+       MOD_DEFS += -DDEBUG_TRACE_INIT
+    endif
+endif
+
+ifeq ("$(OS_KERNEL)", "linux")
+MOD_TYPE = linux_lib
+else
+MOD_TYPE = lib
+endif
+
+# If called by linux kernel builder - add include paths manually.
+# It is not elegant, but we'll not have many linux modules
+ifneq ("$(KBUILD_SRC)", "")
+	-include $(OUT_DIR_BASE)/Makefile.config.$(MOD_NAME)
+endif
+
+# Disable "cast increases required alignment of target type" warning. 
+# There are places in the code with casting from (uint8_t *) to (uint32_t *), but in fact
+# the buffer is well-aligned. 
+EXTRA_CFLAGS += -Wno-error=cast-align
+
+srcs = bcmolt_fld.c
+
+USE_LINT = yes
+
diff --git a/bcm68620_release/release/host_driver/fld/bcm_fld_common.h b/bcm68620_release/release/host_driver/fld/bcm_fld_common.h
new file mode 100644
index 0000000..236c32d
--- /dev/null
+++ b/bcm68620_release/release/host_driver/fld/bcm_fld_common.h
@@ -0,0 +1,245 @@
+/*
+<:copyright-BRCM:2016:DUAL/GPL:standard
+
+   Broadcom Proprietary and Confidential.(c) 2016 Broadcom
+   All Rights Reserved
+
+Unless you and Broadcom execute a separate written software license
+agreement governing use of this software, this software is licensed
+to you under the terms of the GNU General Public License version 2
+(the "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php,
+with the following added to such license:
+
+   As a special exception, the copyright holders of this software give
+   you permission to link this software with independent modules, and
+   to copy and distribute the resulting executable under terms of your
+   choice, provided that you also meet, for each linked independent
+   module, the terms and conditions of the license of that module.
+   An independent module is a module which is not derived from this
+   software.  The special exception does not apply to any modifications
+   of the software.
+
+Not withstanding the above, under no circumstances may you combine
+this software in any way with any other Broadcom software provided
+under a license other than the GPL, without Broadcom's express prior
+written consent.
+
+:>
+ */
+
+#ifndef BCM_FLD_COMMON_H
+#define BCM_FLD_COMMON_H
+
+#define BCM_FLD_SRAM_SIZE                           0x00010000 /* 64 KB */
+
+/******************************/
+/* FLD communication area */
+/******************************/
+#define COMM_WORD_SIZE                              4                   /* 32 bit, 4 byte */
+#define BCM_FLD_COMMUNICATION_AREA_TOP              BCM_FLD_SRAM_SIZE
+
+/* Please do not change PCIE_OPAQUE_DATA_SIZE define, MUST be same as used by pcie dma driver */
+#define PCIE_OPAQUE_DATA_SIZE                       (2*4)               /* two pointers (BD and SBD) */
+
+#define BOOTRECORD_RESERVED                         (2*COMM_WORD_SIZE)  /* 4 words reserved for future needs */
+#define BCM_FLD_CPU_POSTMORTEM_BUF_SIZE             0x00001000
+
+#define BCM_FLD_CPU_STATE_OFFSET                    (BCM_FLD_COMMUNICATION_AREA_TOP       - COMM_WORD_SIZE)     /* 0xfffc */
+#define BCM_FLD_HOST_STATE_OFFSET                   (BCM_FLD_CPU_STATE_OFFSET             - COMM_WORD_SIZE)
+#define BCM_FLD_CPU_DEBUG_STATE_OFFSET              (BCM_FLD_HOST_STATE_OFFSET            - COMM_WORD_SIZE)
+#define BCM_FLD_HOST_DEBUG_STATE_OFFSET             (BCM_FLD_CPU_DEBUG_STATE_OFFSET       - COMM_WORD_SIZE)
+#define BCM_FLD_CPU_BOOTREC_STATE_OFFSET            (BCM_FLD_HOST_DEBUG_STATE_OFFSET      - COMM_WORD_SIZE)
+#define BCM_FLD_HOST_BOOTREC_STATE_OFFSET           (BCM_FLD_CPU_BOOTREC_STATE_OFFSET     - COMM_WORD_SIZE)
+
+#define BCM_FLD_CPU_RESET_REASON_OFFSET             (BCM_FLD_HOST_BOOTREC_STATE_OFFSET    - COMM_WORD_SIZE)
+#define BCM_FLD_CPU_EXCEP_REASON_OFFSET             (BCM_FLD_CPU_RESET_REASON_OFFSET      - COMM_WORD_SIZE)
+#define BCM_FLD_CPU_DDR_MEMC_STATE_OFFSET           (BCM_FLD_CPU_EXCEP_REASON_OFFSET      - COMM_WORD_SIZE)
+#define BCM_FLD_RAS_0_DDR_MEMC_STATE_OFFSET         (BCM_FLD_CPU_DDR_MEMC_STATE_OFFSET    - COMM_WORD_SIZE)
+#define BCM_FLD_RAS_1_DDR_MEMC_STATE_OFFSET         (BCM_FLD_RAS_0_DDR_MEMC_STATE_OFFSET  - COMM_WORD_SIZE)
+
+#define BCM_FLD_CPU_DDR_PHY_STATE_OFFSET            (BCM_FLD_RAS_1_DDR_MEMC_STATE_OFFSET  - COMM_WORD_SIZE)
+#define BCM_FLD_RAS_0_DDR_PHY_STATE_OFFSET          (BCM_FLD_CPU_DDR_PHY_STATE_OFFSET     - 6*COMM_WORD_SIZE)
+#define BCM_FLD_RAS_1_DDR_PHY_STATE_OFFSET          (BCM_FLD_RAS_0_DDR_PHY_STATE_OFFSET   - 6*COMM_WORD_SIZE)
+#define BCM_FLD_BOOT_PROTOCOL_VERSION_OFFSET        (BCM_FLD_RAS_1_DDR_PHY_STATE_OFFSET   - 6*COMM_WORD_SIZE)
+#define BCM_FLD_OS_ENTRY_OFFSET                     (BCM_FLD_BOOT_PROTOCOL_VERSION_OFFSET - COMM_WORD_SIZE)
+#define BCM_FLD_CPU_SET_QUEUES_SIZE                 (BCM_FLD_OS_ENTRY_OFFSET - COMM_WORD_SIZE)
+
+/******************************/
+/* Boot-record  area */
+/******************************/
+/* host write for SoC its rx queue size */
+#define BCM_FLD_HOST_RX_QUEUE_SIZE_OFFSET           (BCM_FLD_CPU_SET_QUEUES_SIZE - COMM_WORD_SIZE)
+#define BCM_FLD_CPU_RX_QUEUE_SIZE_OFFSET            (BCM_FLD_HOST_RX_QUEUE_SIZE_OFFSET - COMM_WORD_SIZE)
+
+#define BCM_FLD_CPU_BOOTRECORD_OFFSET               (BCM_FLD_CPU_RX_QUEUE_SIZE_OFFSET - BOOTRECORD_RESERVED)
+
+#define BCM_FLD_HOST_BOOTRECORD_OFFSET              (BCM_FLD_CPU_BOOTRECORD_OFFSET - PCIE_OPAQUE_DATA_SIZE - BOOTRECORD_RESERVED )
+
+#define BCM_FLD_CPU1_POSTMORTEM_STATE               (BCM_FLD_HOST_BOOTRECORD_OFFSET - COMM_WORD_SIZE)
+#define BCM_FLD_CPU0_POSTMORTEM_STATE               (BCM_FLD_CPU1_POSTMORTEM_STATE - COMM_WORD_SIZE)
+
+#define BCM_FLD_RAS_0_SETTINGS                      (BCM_FLD_CPU0_POSTMORTEM_STATE - COMM_WORD_SIZE)
+#define BCM_FLD_RAS_1_SETTINGS                      (BCM_FLD_RAS_0_SETTINGS - COMM_WORD_SIZE)
+
+#define BCM_RAS_DISABLE                              0x0
+#define BCM_RAS_MODE_GPON                            0x1
+#define BCM_RAS_MODE_XGPON                           0x2
+
+#define BCM_FLD_AVS_SETTINGS                         (BCM_FLD_RAS_1_SETTINGS - COMM_WORD_SIZE)
+#define BCM_FLD_AVS_STOP                             0x0
+#define BCM_FLD_AVS_CONT                             0x1
+
+#ifdef TX_ENABLE_EVENT_TRACE
+#define BCM_FLD_EVENT_TRACE_OFFSET                   (BCM_FLD_AVS_SETTINGS - COMM_WORD_SIZE)
+
+/*********************************************************************************
+ PAY ATTENTION !!! BCM_FLD_COMMUNICATION_AREA_BASE must be equal first byte in the FLD
+            communication area therefore  it should be equal to the last define above
+*********************************************************************************/
+
+#define BCM_FLD_COMMUNICATION_AREA_BASE             BCM_FLD_EVENT_TRACE_OFFSET
+#else
+#define BCM_FLD_COMMUNICATION_AREA_BASE             BCM_FLD_RAS_1_SETTINGS
+#endif
+#define BCM_FLD_COMMUNICATION_AREA_SIZE             BCM_FLD_COMMUNICATION_AREA_TOP - BCM_FLD_COMMUNICATION_AREA_BASE
+
+/*********************************************************************************
+ PAY ATTENTION !!! POSTMORTEM_BUF_OFFSET must be outside the communication area
+             therefore  it should be defined from BCM_FLD_COMMUNICATION_AREA_BASE
+*********************************************************************************/
+
+#define BCM_FLD_CPU1_POSTMORTEM_BUF_OFFSET          (BCM_FLD_COMMUNICATION_AREA_BASE - BCM_FLD_CPU_POSTMORTEM_BUF_SIZE)
+#define BCM_FLD_CPU0_POSTMORTEM_BUF_OFFSET          (BCM_FLD_CPU1_POSTMORTEM_BUF_OFFSET - BCM_FLD_CPU_POSTMORTEM_BUF_SIZE)
+#define BCM_FLD_HOST_EVENT                          (BCM_FLD_CPU0_POSTMORTEM_BUF_OFFSET - COMM_WORD_SIZE)
+
+#define BCM_FLD_DDR_TEST_RESULTS_SIZE               (3 * COMM_WORD_SIZE) /* CPU + RAS 0 + RAS 1 */
+#define BCM_FLD_DDR_TEST_RESULTS                    (BCM_FLD_HOST_EVENT - BCM_FLD_DDR_TEST_RESULTS_SIZE)
+
+/* SW Error table */
+#define BCM_FLD_SW_ERROR_TABLE_SIZE                 (1171 * COMM_WORD_SIZE)
+#define BCM_FLD_SW_ERROR_TABLE                      (BCM_FLD_DDR_TEST_RESULTS - BCM_FLD_SW_ERROR_TABLE_SIZE)
+
+/* logger will NOT overwrite other fields */
+#define BCM_FLD_LOGGER_TOP                          BCM_FLD_SW_ERROR_TABLE
+#define BCM_FLD_LOGGER_BASE                         0 /* logger will overwrite the bootloader */
+
+/* BCM68620 (Maple) functional states */
+#define BCM_FLD_CPU_FINISH_BOOTLOADER_SHIFT         0
+#define BCM_FLD_CPU_FINISH_BOOTLOADER_MASK          (0x1 << BCM_FLD_CPU_FINISH_BOOTLOADER_SHIFT)
+
+#define BCM_FLD_CPU_READY_SHIFT                     1
+#define BCM_FLD_CPU_READY_MASK                      (0x1 << BCM_FLD_CPU_READY_SHIFT)
+
+#define BCM_FLD_DDR_TEST_DONE_SHIFT                 2
+#define BCM_FLD_DDR_TEST_DONE_MASK                  (0x1 << BCM_FLD_DDR_TEST_DONE_SHIFT)
+
+/* BCM68620 (Host) functional states */
+#define BCM_FLD_HOST_FINISH_WRITE_DDR_SHIFT         0
+#define BCM_FLD_HOST_FINISH_WRITE_DDR_MASK          (0x1 << BCM_FLD_HOST_FINISH_WRITE_DDR_SHIFT)
+
+#define BCM_FLD_HOST_RUN_CPU_DDR_TEST_SHIFT         1
+#define BCM_FLD_HOST_RUN_CPU_DDR_TEST_MASK          (0x1 << BCM_FLD_HOST_RUN_CPU_DDR_TEST_SHIFT)
+
+#define BCM_FLD_HOST_RUN_RAS_0_TEST_SHIFT           2
+#define BCM_FLD_HOST_RUN_RAS_0_TEST_MASK            (0x1 << BCM_FLD_HOST_RUN_RAS_0_TEST_SHIFT)
+
+#define BCM_FLD_HOST_RUN_RAS_1_TEST_SHIFT           3
+#define BCM_FLD_HOST_RUN_RAS_1_TEST_MASK            (0x1 << BCM_FLD_HOST_RUN_RAS_1_TEST_SHIFT)
+
+/* host bootrecord states */
+#define BCM_FLD_HOST_PRM_VALID_SHIFT                0
+#define BCM_FLD_HOST_PRM_VALID_MASK                 (0x1 << BCM_FLD_HOST_PRM_VALID_SHIFT)
+
+/* device bootrecord states */
+#define BCM_FLD_CPU_PRM_VALID_SHIFT                 0
+#define BCM_FLD_CPU_PRM_VALID_MASK                  (0x1 << BCM_FLD_CPU_PRM_VALID_SHIFT)
+
+/* queue validity flag */
+#define BCM_FLD_CPU_QUEUE_VALID_SHIFT               0
+#define BCM_FLD_CPU_QUEUE_VALID_MASK                (0x1 << BCM_FLD_CPU_QUEUE_VALID_SHIFT)
+
+/* CPU debug states */
+#define CPU_DEBUG_BOOT_FLASH        (1<<0)
+#define CPU_DEBUG_RUN__FROM_SRAM    (1<<1)
+#define CPU_DEBUG_LUT_DONE          (1<<2)
+#define CPU_DEBUG_B15_CFG_DONE      (1<<3)
+#define CPU_DEBUG_UART_INIT_DONE    (1<<4)
+#define CPU_DEBUG_CLEAR_BSS_DONE    (1<<5)
+#define CPU_DEBUG_RUN_C             (1<<6)
+#define CPU_DEBUG_FLASH_READ_FAILED (1<<7)
+#define CPU_DEBUG_OS_FAILED         (1<<8)
+
+/* CPU exception reason */
+#define CPU_EXCEP_UNDEF_INSTR       (1<<0)
+#define CPU_EXCEP_SW_INTR           (1<<1)
+#define CPU_EXCEP_PREFETCH_ABORT    (1<<2)
+#define CPU_EXCEP_DATA_ABORT        (1<<3)
+#define CPU_EXCEP_IRQ               (1<<4)
+#define CPU_EXCEP_FIQ               (1<<5)
+
+#ifndef __ASSEMBLER__
+/* SoC states values */
+typedef enum
+{
+    BCM_FLD_CPU_STATE_UNKNOWN,
+    BCM_FLD_SRAM_BOOT_DONE,
+    BCM_FLD_BOOT_FROM_DDR,
+    BCM_FLD_RUN_FROM_DDR,
+    BCM_FLD_CPU_READY,
+    BCM_FLD_HOST_READY,
+    BCM_FLD_CPU_FINISH_BOOTLOADER
+} BCM_FLD_CPU_STATE;
+
+/* SoC reset values */
+typedef enum
+{
+    BCM_FLD_CPU_RESET_UNKNOWN
+} BCM_FLD_CPU_RESET_REASON;
+
+typedef enum
+{
+    BCM_FLD_RAS_MODE_NOT_CONFIGURED,
+    BCM_FLD_RAS_MODE_GPON,
+    BCM_FLD_RAS_MODE_XGPON,
+    BCM_FLD_RAS_MODE_XGS_NGPON2,
+} BCM_FLD_RSM_MODE;
+
+typedef struct
+{
+    unsigned int magic;
+    unsigned int msg_len;
+    char msg[1];
+} BCM_FLD_POSTMORTEM_LOG;
+#endif
+
+#define BCM_FLD_POSTMORTEM_LOG_MAGIC      0xFEEDBACC
+
+/* device_debug_states */
+#define BCM_FLD_CPU_BOOT_FROM_SRAM_STATES_SHIFT     0
+#define BCM_FLD_CPU_BOOT_FROM_SRAM_STATES_MASK      0x000000ffU
+#define BCM_FLD_CPU_BOOT_FROM_SRAM_ERRORS_SHIFT     8
+#define BCM_FLD_CPU_BOOT_FROM_SRAM_ERRORS_MASK      0x0000ff00U
+#define BCM_FLD_CPU_BOOT_FROM_SRAM_EXCEPTION_SHIFT  16
+#define BCM_FLD_CPU_BOOT_FROM_SRAM_EXCEPTION_MASK   0x00ff0000U
+#define BCM_FLD_CPU_RUN_FROM_DDR_STATES_SHIFT       24
+#define BCM_FLD_CPU_RUN_FROM_DDR_STATES_MASK        0xff000000U
+/* host_debug_states */
+#define BCM_FLD_HOST_WRITE_SRAM_SHIFT               0
+#define BCM_FLD_HOST_WRITE_SRAM_MASK                0x00000001U
+#define BCM_FLD_HOST_START_CPU_SHIFT                1
+#define BCM_FLD_HOST_START_CPU_MASK                 0x00000002U
+#define BCM_FLD_HOST_WRITE_DDR_SHIFT                2
+#define BCM_FLD_HOST_WRITE_DDR_MASK                 0x00000004U
+
+#define CPU_2_PCIE_MEM_WIN0_BASE    0x90000000
+#define CPU_2_PCIE_MEM_WIN0_SIZE    0x00100000
+#define MAX_PMC_SIZE                0x8000
+
+#ifdef TX_ENABLE_EVENT_TRACE
+#define EVENT_BUFFER_SIZE           0x00600000 /* 6 Mbyte */
+/* leave 1 Mbyte gap between windows */
+#define CPU_2_PCIE_MEM_WIN1_BASE    CPU_2_PCIE_MEM_WIN0_BASE + CPU_2_PCIE_MEM_WIN0_SIZE + 0x100000
+#define CPU_2_PCIE_MEM_WIN1_SIZE    EVENT_BUFFER_SIZE
+#endif
+
+#endif
diff --git a/bcm68620_release/release/host_driver/fld/bcmolt_fld.c b/bcm68620_release/release/host_driver/fld/bcmolt_fld.c
new file mode 100644
index 0000000..d4e92b2
--- /dev/null
+++ b/bcm68620_release/release/host_driver/fld/bcmolt_fld.c
@@ -0,0 +1,850 @@
+/*
+<:copyright-BRCM:2016:DUAL/GPL:standard
+
+   Broadcom Proprietary and Confidential.(c) 2016 Broadcom
+   All Rights Reserved
+
+Unless you and Broadcom execute a separate written software license
+agreement governing use of this software, this software is licensed
+to you under the terms of the GNU General Public License version 2
+(the "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php,
+with the following added to such license:
+
+   As a special exception, the copyright holders of this software give
+   you permission to link this software with independent modules, and
+   to copy and distribute the resulting executable under terms of your
+   choice, provided that you also meet, for each linked independent
+   module, the terms and conditions of the license of that module.
+   An independent module is a module which is not derived from this
+   software.  The special exception does not apply to any modifications
+   of the software.
+
+Not withstanding the above, under no circumstances may you combine
+this software in any way with any other Broadcom software provided
+under a license other than the GPL, without Broadcom's express prior
+written consent.
+
+:>
+ */
+
+#include "bcmolt_fld.h"
+#ifdef TX_ENABLE_EVENT_TRACE
+#include "bcmolt_llpcie.h"
+#endif
+
+/* internal data base */
+static uint32_t max_bcm68620_device = 0;
+static bcm_fld_device_info *bcm68620_info = NULL;
+
+#define SRAM_ADDRESS(device,offset) (uint32_t *)(bcm68620_info[device].soc_sram_base + offset)
+
+bcmos_errno bcm_fld_init(uint32_t max_devices)
+{
+    max_bcm68620_device = max_devices;
+    bcm68620_info = (bcm_fld_device_info *)bcmos_alloc(max_devices * sizeof(bcm_fld_device_info));
+    if (!bcm68620_info)
+        return BCM_ERR_NOMEM;
+    memset(bcm68620_info, 0, max_devices * sizeof(bcm_fld_device_info));
+
+    return BCM_ERR_OK;
+}
+
+void bcm_fld_clear_comm_area(uint32_t device)
+{
+    memset((char *)SRAM_ADDRESS(device,BCM_FLD_COMMUNICATION_AREA_BASE), 0 ,BCM_FLD_COMMUNICATION_AREA_SIZE);
+#if defined(TX_ENABLE_EVENT_TRACE) && defined(DEBUG_TRACE_INIT)
+    bcm_ll_pcie_setrace(device);
+#endif
+}
+
+bcmos_errno bcm_fld_exit(void)
+{
+    if (bcm68620_info)
+        bcmos_free(bcm68620_info);
+
+    bcm68620_info = NULL;
+
+    return BCM_ERR_OK;
+}
+
+/* register a device to driver
+   returns the driver index, instead the user's
+   store the user,s information about the device */
+bcmos_errno bcm_fld_register(uint32_t device, bcm_fld_device_info *info)
+{
+    if (!info)
+        return BCM_ERR_PARM;
+
+    if (!bcm68620_info)
+        return BCM_ERR_NORES;
+
+    if (device >= max_bcm68620_device)
+        return BCM_ERR_RANGE;
+
+    if (bcm68620_info[device].soc_sram_base)
+        return BCM_ERR_ALREADY;
+
+    /* copy the information received from the user to uint32_ternal data base */
+    bcm68620_info[device].soc_sram_base = info->soc_sram_base;
+    bcm68620_info[device].soc_ddr_base = info->soc_ddr_base;
+    bcm68620_info[device].soc_regs_base = info->soc_regs_base;
+    bcm68620_info[device].soc_ddr_length = info->soc_ddr_length;
+
+    return BCM_ERR_OK;
+}
+
+/* remove a device from uint32_ternal data base */
+bcmos_errno bcm_fld_unregister(uint32_t device)
+{
+    if (!bcm68620_info)
+        return BCM_ERR_NORES;
+
+    if (device >= max_bcm68620_device)
+        return BCM_ERR_RANGE;
+
+    /* clear the uint32_ternal data base for the given device */
+    bcm68620_info[device].soc_sram_base = 0;
+    bcm68620_info[device].soc_ddr_base = 0;
+    bcm68620_info[device].soc_ddr_length = 0;
+    bcm68620_info[device].soc_crt_length = 0;
+    bcm68620_info[device].soc_regs_base = 0;
+
+    return BCM_ERR_OK;
+}
+
+/* read from communication area and return the soc state
+   reset reason and protocol version */
+bcmos_errno bcm_fld_get_device_status(uint32_t device, bcm_fld_device_stat *debug_state)
+{
+    if (!debug_state)
+        return BCM_ERR_PARM;
+
+    if (!bcm68620_info)
+        return BCM_ERR_NORES;
+
+    if (device >= max_bcm68620_device)
+        return BCM_ERR_RANGE;
+
+    /* read from SRAM os entry offset, CPU status, reason and protocol version */
+    debug_state->protocol_version   = bcm_pci_read32(SRAM_ADDRESS(device,BCM_FLD_BOOT_PROTOCOL_VERSION_OFFSET));
+    debug_state->state              = bcm_pci_read32(SRAM_ADDRESS(device,BCM_FLD_CPU_STATE_OFFSET));
+    debug_state->reason             = bcm_pci_read32(SRAM_ADDRESS(device,BCM_FLD_CPU_RESET_REASON_OFFSET));
+    debug_state->os_entry_offset    = bcm_pci_read32(SRAM_ADDRESS(device,BCM_FLD_OS_ENTRY_OFFSET));
+
+    return BCM_ERR_OK;
+}
+
+/* returns the last soc state */
+bcmos_errno bcm_fld_get_device_loading_state(uint32_t device, BCM_FLD_CPU_STATE *cpu_state)
+{
+    uint32_t temp;
+    volatile uint32_t value;
+
+    if (!cpu_state)
+        return BCM_ERR_PARM;
+
+    if (!bcm68620_info)
+        return BCM_ERR_NORES;
+
+    if (device >= max_bcm68620_device)
+        return BCM_ERR_RANGE;
+
+    value = bcm_pci_read32(SRAM_ADDRESS(device,BCM_FLD_CPU_STATE_OFFSET));
+    temp = value & BCM_FLD_CPU_READY_MASK;
+    if (temp)
+        *cpu_state = BCM_FLD_CPU_READY;
+    else
+    {
+        temp = value & BCM_FLD_CPU_FINISH_BOOTLOADER_MASK;
+        if (temp)
+            *cpu_state = BCM_FLD_CPU_FINISH_BOOTLOADER;
+        else
+            *cpu_state = BCM_FLD_CPU_STATE_UNKNOWN;
+    }
+
+    return BCM_ERR_OK;
+}
+
+/* write in communication area the current host status during loading process */
+bcmos_errno bcm_fld_host_finish_write_ddr(uint32_t device, uint32_t os_entry_address)
+{
+    if (!bcm68620_info)
+        return BCM_ERR_NORES;
+
+    if (device >= max_bcm68620_device)
+        return BCM_ERR_RANGE;
+
+    /* write os_entry address of the code from DDR */
+    bcm_pci_write32(SRAM_ADDRESS(device,BCM_FLD_OS_ENTRY_OFFSET), os_entry_address);
+    /* run code from DDR */
+    bcm_pci_write32(SRAM_ADDRESS(device,BCM_FLD_HOST_STATE_OFFSET), BCM_FLD_HOST_FINISH_WRITE_DDR_MASK);
+
+    return BCM_ERR_OK;
+}
+
+/* return the logs area */
+bcmos_errno bcm_fld_get_logs(uint32_t device, char **log_area, int *length)
+{
+    if (!log_area || !length)
+        return BCM_ERR_PARM;
+
+    if (!bcm68620_info)
+        return BCM_ERR_NORES;
+
+    if (device >= max_bcm68620_device)
+        return BCM_ERR_RANGE;
+
+    *log_area = (char *)SRAM_ADDRESS(device, BCM_FLD_LOGGER_BASE);
+    *length = BCM_FLD_LOGGER_TOP;
+
+    return BCM_ERR_OK;
+}
+
+/* write the received buffer to memory according to offset and type */
+bcmos_errno bcm_fld_write(uint32_t device, char *buff, uint32_t buff_size, uint32_t offset_in_image, bcmolt_device_image_type image_type)
+{
+    unsigned long address = 0;
+    int i;
+#ifndef PCIE_BYTE_COPY
+    uint32_t size, rest;
+    uint32_t* buff_32;
+    uint32_t* addr_32;
+#endif
+
+    if (!buff)
+        return BCM_ERR_PARM;
+
+    if (!bcm68620_info)
+        return BCM_ERR_NORES;
+
+    if (device >= max_bcm68620_device)
+        return BCM_ERR_RANGE;
+
+    if (image_type == BCMOLT_DEVICE_IMAGE_TYPE_BOOTLOADER)
+    {
+        address = bcm68620_info[device].soc_sram_base + offset_in_image;
+        if ((offset_in_image + buff_size) > BCM_FLD_COMMUNICATION_AREA_BASE)
+            return BCM_ERR_OVERFLOW;
+    }
+    else if (image_type == BCMOLT_DEVICE_IMAGE_TYPE_APPLICATION)
+    {
+        address = bcm68620_info[device].soc_ddr_base + offset_in_image;
+        if ((offset_in_image + buff_size) > bcm68620_info[device].soc_ddr_length)
+            return BCM_ERR_OVERFLOW;
+        bcm68620_info[device].soc_crt_length += buff_size;
+    }
+    else
+    {
+        return BCM_ERR_PARM;
+    }
+
+#ifndef PCIE_BYTE_COPY
+    size = buff_size / sizeof(*buff_32);
+    rest = buff_size & (sizeof(*buff_32) -1);
+
+    buff_32 = (uint32_t*)buff;
+    addr_32 = (uint32_t*)address;
+
+    if (rest)
+        size++;
+    for(i = 0; i < size; i++)
+        bcm_pci_write32((addr_32 + i),BCMOS_ENDIAN_CPU_TO_LITTLE_U32(*(buff_32 +i)));
+#else
+    for (i = 0; i < buff_size; i++)
+        *(uint8_t *)(address + i) = buff[i];
+#endif
+
+    bcmos_barrier();
+
+    return BCM_ERR_OK;
+}
+
+/* read to the received buffer from memory according to offset and type */
+bcmos_errno bcm_fld_read(uint32_t device, char *buff, uint32_t *buff_size, uint32_t offset_in_image, bcmolt_device_image_type image_type)
+{
+    unsigned long address = 0;
+    uint32_t i;
+#ifndef PCIE_BYTE_COPY
+    uint32_t size, rest;
+    uint32_t* buff_32;
+    uint32_t* addr_32;
+#endif
+
+    if (!buff || !buff_size)
+        return BCM_ERR_PARM;
+
+    if (!bcm68620_info)
+        return BCM_ERR_NORES;
+
+    if (device >= max_bcm68620_device)
+        return BCM_ERR_RANGE;
+
+    if(image_type == BCMOLT_DEVICE_IMAGE_TYPE_BOOTLOADER)
+        address = bcm68620_info[device].soc_sram_base + offset_in_image;
+    else if (image_type == BCMOLT_DEVICE_IMAGE_TYPE_APPLICATION)
+        address = bcm68620_info[device].soc_ddr_base + offset_in_image;
+    else
+        return BCM_ERR_PARM;
+
+    /* temporary for test , consider to integrate in future */
+#ifndef PCIE_BYTE_COPY
+    size = *buff_size /sizeof(*buff_32);
+    rest = *buff_size & (sizeof(*buff_32) -1);
+    buff_32 = (uint32_t*)buff;
+    addr_32 = (uint32_t*)address;
+
+    if (rest)
+        size++;
+    for(i = 0; i < size; i++)
+        *(buff_32 +i)= BCMOS_ENDIAN_CPU_TO_LITTLE_U32(bcm_pci_read32((uint32_t *)(addr_32 + i)));
+#else
+    for (i = 0; i < *buff_size; i++)
+        buff[i] = *(uint8_t *)(address + i);
+
+#endif
+
+    bcmos_barrier();
+
+    return BCM_ERR_OK;
+}
+
+
+/*********** PMC definitions ****************/
+#define PMC_QUEUE_0_DATA_UNRESET0   0x401c00U
+#define PMC_QUEUE_0_DATA_UNRESET1   0x401c04U
+#define PMC_QUEUE_0_DATA_UNRESET2   0x401c08U
+#define PMC_QUEUE_0_DATA_UNRESET3   0x401c0cU
+
+#define PMC_QUEUE_1_DATA_UNRESET0   0x401c10U
+#define PMC_QUEUE_1_DATA_UNRESET1   0x401c14U
+#define PMC_QUEUE_1_DATA_UNRESET2   0x401c18U
+#define PMC_QUEUE_1_DATA_UNRESET3   0x401c1cU
+
+#define PMC_CNTRL_HOST_MBOX_IN      0x401028U
+#define PMC_HOST_MBOX_MASK          0x2
+#define PMC_PMB_CNTRL               0x4800c0U
+/* The below value is the swap of ((1 << 31) | (1<<20) | (4 << 12) | (0x0C)) */
+#define PMC_PMB_CMD                 0x0C401080
+#define PMC_PMB_WRITE               0x4800c4U
+/* The below value is the swap of 0x1*/
+#define PMC_PMB_ADDRESS             0x1000000
+
+/* PMC command to take ARM out of reset */
+#define ARM_OUT_OF_RESET            35
+/********************************************/
+
+bcmos_errno bcm_fld_start_bootloader(uint32_t device, uint32_t test_ddr)
+{
+/* temporary disabled: just for A0, should be enabled in B0
+#ifdef BCM_PMC_EXIST
+    volatile uint32_t readval;
+#endif
+*/
+    if (!bcm68620_info)
+        return BCM_ERR_NORES;
+
+    if (device >= max_bcm68620_device)
+        return BCM_ERR_RANGE;
+
+    bcm_pci_write32(SRAM_ADDRESS(device, BCM_FLD_HOST_STATE_OFFSET), test_ddr);
+    /* start processor */
+    bcm_fld_set_host_debug_status(device, BCM_FLD_HOST_START_CPU);
+/* Temporary disabled - should be enabled in B0
+#ifndef BCM_PMC_EXIST */
+    bcm_pci_read32((uint32_t *)(bcm68620_info[device].soc_regs_base + PMC_PMB_CNTRL));
+    bcm_pci_write32((uint32_t *)(bcm68620_info[device].soc_regs_base + PMC_PMB_WRITE), PMC_PMB_ADDRESS);
+    bcm_pci_read32((uint32_t *)(bcm68620_info[device].soc_regs_base + PMC_PMB_WRITE));
+    bcm_pci_write32((uint32_t *)(bcm68620_info[device].soc_regs_base + PMC_PMB_CNTRL), PMC_PMB_CMD);
+    bcm_pci_read32((uint32_t *)(bcm68620_info[device].soc_regs_base + PMC_PMB_CNTRL));
+/*
+#else
+    readval = bcm_pci_read32((uint32_t *)(bcm68620_info[device].soc_regs_base + PMC_CNTRL_HOST_MBOX_IN));
+    if (!(readval & PMC_HOST_MBOX_MASK))
+        return BCM_ERR_NOT_CONNECTED;
+
+    bcm_pci_write32((bcm68620_info[device].soc_regs_base + PMC_QUEUE_0_DATA_UNRESET0), BCMOS_ENDIAN_CPU_TO_LITTLE_U32(ARM_OUT_OF_RESET));
+    bcm_pci_write32((bcm68620_info[device].soc_regs_base + PMC_QUEUE_0_DATA_UNRESET1), BCMOS_ENDIAN_CPU_TO_LITTLE_U32(0));
+    bcm_pci_write32((bcm68620_info[device].soc_regs_base + PMC_QUEUE_0_DATA_UNRESET2), BCMOS_ENDIAN_CPU_TO_LITTLE_U32(0));
+    bcm_pci_write32((bcm68620_info[device].soc_regs_base + PMC_QUEUE_0_DATA_UNRESET3), BCMOS_ENDIAN_CPU_TO_LITTLE_U32(0));
+    bcmos_usleep(10000); // 10 msec
+    // read PMC response, to clean the queue
+    bcm_pci_read32((uint32_t *)(bcm68620_info[device].soc_regs_base + PMC_QUEUE_1_DATA_UNRESET0));
+    bcm_pci_read32((uint32_t *)(bcm68620_info[device].soc_regs_base + PMC_QUEUE_1_DATA_UNRESET1));
+    bcm_pci_read32((uint32_t *)(bcm68620_info[device].soc_regs_base + PMC_QUEUE_1_DATA_UNRESET2));
+    bcm_pci_read32((uint32_t *)(bcm68620_info[device].soc_regs_base + PMC_QUEUE_1_DATA_UNRESET3));
+#endif
+*/
+
+    return BCM_ERR_OK;
+}
+
+bcmos_bool bcm_fld_is_bootloader_done(uint32_t device)
+{
+    volatile uint32_t value;
+
+    if (!bcm68620_info)
+        return BCMOS_FALSE;
+
+    if (device >= max_bcm68620_device)
+        return BCMOS_FALSE;
+
+    value = bcm_pci_read32(SRAM_ADDRESS(device,BCM_FLD_CPU_STATE_OFFSET));
+    if (value & BCM_FLD_CPU_FINISH_BOOTLOADER_MASK)
+        return BCMOS_TRUE;
+
+    return BCMOS_FALSE;
+}
+
+bcmos_bool bcm_fld_is_ddr_test_done(uint32_t device)
+{
+    uint32_t value = bcm_pci_read32(SRAM_ADDRESS(device, BCM_FLD_CPU_STATE_OFFSET));
+    return 0 != (value & BCM_FLD_DDR_TEST_DONE_MASK);
+}
+
+bcmos_bool bcm_fld_test_device_bootrecord_flag(uint32_t device)
+{
+    volatile uint32_t value;
+
+    if (!bcm68620_info)
+        return BCMOS_FALSE;
+
+    if (device >= max_bcm68620_device)
+        return BCMOS_FALSE;
+
+    value = bcm_pci_read32(SRAM_ADDRESS(device,BCM_FLD_CPU_BOOTREC_STATE_OFFSET));
+    if (value & BCM_FLD_CPU_PRM_VALID_MASK)
+        return BCMOS_TRUE;
+
+    return BCMOS_FALSE;
+}
+
+bcmos_errno bcm_fld_get_device_bootrecord(uint32_t device, uint32_t *opaque_data)
+{
+    uint32_t *addr, *temp;
+    int32_t i;
+
+    if (!opaque_data)
+        return BCM_ERR_PARM;
+
+    if (!bcm68620_info)
+        return BCM_ERR_NORES;
+
+    if (device >= max_bcm68620_device)
+        return BCM_ERR_RANGE;
+
+    temp = opaque_data;
+    addr = SRAM_ADDRESS(device,BCM_FLD_CPU_BOOTRECORD_OFFSET);
+    for (i = 0; i < PCIE_OPAQUE_DATA_SIZE / 4; i++)
+    {
+        *temp++ = bcm_pci_read32(addr++);
+    }
+
+    return BCM_ERR_OK;
+}
+
+bcmos_errno bcm_fld_clear_device_bootrecord_flag(uint32_t device)
+{
+    volatile uint32_t value;
+
+    if (!bcm68620_info)
+        return BCM_ERR_NORES;
+
+    if (device >= max_bcm68620_device)
+        return BCM_ERR_RANGE;
+
+    /* clear SoC prm valid bit */
+    value = bcm_pci_read32(SRAM_ADDRESS(device,BCM_FLD_CPU_BOOTREC_STATE_OFFSET));
+    value &= ~BCM_FLD_CPU_PRM_VALID_MASK;
+    bcm_pci_write32(SRAM_ADDRESS(device,BCM_FLD_CPU_BOOTREC_STATE_OFFSET), value);
+
+    return BCM_ERR_OK;
+}
+
+bcmos_errno bcm_fld_set_host_bootrecord_flag(uint32_t device)
+{
+    volatile uint32_t value;
+
+    if (!bcm68620_info)
+        return BCM_ERR_NORES;
+
+    if (device >= max_bcm68620_device)
+        return BCM_ERR_RANGE;
+
+    /* set host prm valid bit */
+    value = bcm_pci_read32(SRAM_ADDRESS(device,BCM_FLD_HOST_BOOTREC_STATE_OFFSET));
+    value |= ((1 << BCM_FLD_HOST_PRM_VALID_SHIFT) & BCM_FLD_HOST_PRM_VALID_MASK);
+    bcm_pci_write32(SRAM_ADDRESS(device,BCM_FLD_HOST_BOOTREC_STATE_OFFSET), value);
+
+    return BCM_ERR_OK;
+}
+
+bcmos_bool bcm_fld_test_host_bootrecord_flag(uint32_t device)
+{
+    volatile uint32_t value;
+
+    if (!bcm68620_info)
+        return BCMOS_FALSE;
+
+    if (device >= max_bcm68620_device)
+        return BCMOS_FALSE;
+
+    value = bcm_pci_read32(SRAM_ADDRESS(device,BCM_FLD_HOST_BOOTREC_STATE_OFFSET));
+    if (value & BCM_FLD_HOST_PRM_VALID_MASK)
+        return BCMOS_TRUE;
+
+    return BCMOS_FALSE;
+}
+
+bcmos_errno bcm_fld_set_rings_size(uint32_t device, uint32_t host_tx_size, uint32_t host_rx_size)
+{
+    volatile uint32_t value;
+
+    if (!bcm68620_info)
+        return BCM_ERR_NORES;
+
+    if (device >= max_bcm68620_device)
+        return BCM_ERR_RANGE;
+
+    /* write host_pd_ring_size to communication area - SoC will use it in first stages of application */
+    /* device tx ring size is the same as host rx queue */
+    bcm_pci_write32(SRAM_ADDRESS(device,BCM_FLD_HOST_RX_QUEUE_SIZE_OFFSET), host_rx_size);
+    /* device rx ring size is the same as host tx queue */
+    bcm_pci_write32(SRAM_ADDRESS(device,BCM_FLD_CPU_RX_QUEUE_SIZE_OFFSET), host_tx_size);
+    /* set host queue valid bit */
+    value = bcm_pci_read32(SRAM_ADDRESS(device,BCM_FLD_CPU_SET_QUEUES_SIZE));
+    value |= ((1 << BCM_FLD_CPU_QUEUE_VALID_SHIFT) & BCM_FLD_CPU_QUEUE_VALID_MASK);
+    bcm_pci_write32(SRAM_ADDRESS(device,BCM_FLD_CPU_SET_QUEUES_SIZE), value);
+
+    return BCM_ERR_OK;
+}
+
+bcmos_errno bcm_fld_get_exception_state(uint32_t device, uint32_t *state0, uint32_t *state1)
+{
+    if (!bcm68620_info)
+        return BCM_ERR_NORES;
+
+    if (device >= max_bcm68620_device)
+        return BCM_ERR_RANGE;
+
+    if (!state0 || !state1)
+        return BCM_ERR_PARM;
+
+    *state0 = bcm_pci_read32(SRAM_ADDRESS(device, BCM_FLD_CPU0_POSTMORTEM_STATE));
+    *state1 = bcm_pci_read32(SRAM_ADDRESS(device, BCM_FLD_CPU1_POSTMORTEM_STATE));
+
+    return BCM_ERR_OK;
+}
+
+bcmos_errno bcm_fld_clear_exception_state(uint32_t device, uint32_t cpuid)
+{
+
+    uint32_t offset =  cpuid ? BCM_FLD_CPU1_POSTMORTEM_STATE : BCM_FLD_CPU0_POSTMORTEM_STATE;
+
+    if (!bcm68620_info)
+        return BCM_ERR_NORES;
+
+    if ((device >= max_bcm68620_device) || (cpuid > 1))
+        return BCM_ERR_RANGE;
+
+    bcm_pci_write32(SRAM_ADDRESS(device, offset), 0);
+
+    return BCM_ERR_OK;
+}
+
+bcmos_errno bcm_fld_copy_exception_log(uint32_t device, uint32_t cpuid, char *buffer, int *length)
+{
+    BCM_FLD_POSTMORTEM_LOG *exlog;
+    uint32_t offset =  cpuid ? BCM_FLD_CPU1_POSTMORTEM_BUF_OFFSET : BCM_FLD_CPU0_POSTMORTEM_BUF_OFFSET;
+
+    if (!bcm68620_info)
+        return BCM_ERR_NORES;
+
+    if ((device >= max_bcm68620_device) || (cpuid > 1))
+        return BCM_ERR_RANGE;
+
+    if (!buffer || !length)
+        return BCM_ERR_PARM;
+
+    exlog = (BCM_FLD_POSTMORTEM_LOG *)SRAM_ADDRESS(device, offset);
+    if (exlog->magic != BCM_FLD_POSTMORTEM_LOG_MAGIC)
+        *length = 0;
+    else
+    {
+        int i;
+        *length = exlog->msg_len;
+        /* if host is 64 bit and bigendian memcpy does not work correctly */
+        for (i=0; i < exlog->msg_len; i++)
+        {
+            buffer[i] = exlog->msg[i];
+        }
+    }
+    buffer[*length] = '\0';
+
+    return BCM_ERR_OK;
+}
+
+/**
+* \Debug states and functions
+*/
+bcmos_errno bcm_fld_get_device_debug_status(uint32_t device, bcm_fld_device_debug_state *info)
+{
+    volatile uint32_t value;
+
+    if (!info)
+        return BCM_ERR_PARM;
+
+    if (!bcm68620_info)
+        return BCM_ERR_NORES;
+
+    if (device >= max_bcm68620_device)
+        return BCM_ERR_RANGE;
+
+    value = bcm_pci_read32(SRAM_ADDRESS(device,BCM_FLD_CPU_DEBUG_STATE_OFFSET));
+    info->boot_from_sram_states = (value & BCM_FLD_CPU_BOOT_FROM_SRAM_STATES_MASK) >> BCM_FLD_CPU_BOOT_FROM_SRAM_STATES_SHIFT;
+    info->boot_from_sram_errors = (value & BCM_FLD_CPU_BOOT_FROM_SRAM_ERRORS_MASK) >> BCM_FLD_CPU_BOOT_FROM_SRAM_ERRORS_SHIFT;
+    info->boot_from_sram_exception = (value & BCM_FLD_CPU_BOOT_FROM_SRAM_EXCEPTION_MASK) >> BCM_FLD_CPU_BOOT_FROM_SRAM_EXCEPTION_SHIFT;
+    info->run_from_ddr_state = (value & BCM_FLD_CPU_RUN_FROM_DDR_STATES_MASK) >> BCM_FLD_CPU_RUN_FROM_DDR_STATES_SHIFT;
+
+    return BCM_ERR_OK;
+}
+
+bcmos_errno bcm_fld_get_host_debug_status(uint32_t device, bcm_fld_host_debug_state *info)
+{
+    volatile uint32_t value;
+
+    if (!info)
+        return BCM_ERR_PARM;
+
+    if (!bcm68620_info)
+        return BCM_ERR_NORES;
+
+    if (device >= max_bcm68620_device)
+        return BCM_ERR_RANGE;
+
+    value = bcm_pci_read32(SRAM_ADDRESS(device,BCM_FLD_HOST_DEBUG_STATE_OFFSET));
+    info->write_sram = (value & BCM_FLD_HOST_WRITE_SRAM_MASK) >> BCM_FLD_HOST_WRITE_SRAM_SHIFT;
+    info->start_device = (value & BCM_FLD_HOST_START_CPU_MASK) >> BCM_FLD_HOST_START_CPU_SHIFT;
+    info->write_ddr = (value & BCM_FLD_HOST_WRITE_DDR_MASK) >> BCM_FLD_HOST_WRITE_DDR_SHIFT;
+    value = bcm_pci_read32(SRAM_ADDRESS(device,BCM_FLD_HOST_STATE_OFFSET));
+    info->finish_ddr = (value & BCM_FLD_HOST_FINISH_WRITE_DDR_MASK) >> BCM_FLD_HOST_FINISH_WRITE_DDR_SHIFT;
+
+    return BCM_ERR_OK;
+}
+
+bcmos_errno bcm_fld_set_host_debug_status(uint32_t device, BCM_FLD_HOST_DEBUG_VALUES stat)
+{
+    volatile uint32_t value = 0;
+
+    if (!bcm68620_info)
+        return BCM_ERR_NORES;
+
+    if (device >= max_bcm68620_device)
+        return BCM_ERR_RANGE;
+
+    if (stat == BCM_FLD_HOST_WRITE_SRAM)
+        value = ((1 << BCM_FLD_HOST_WRITE_SRAM_SHIFT) & BCM_FLD_HOST_WRITE_SRAM_MASK);
+    else
+    {
+        value = bcm_pci_read32(SRAM_ADDRESS(device,BCM_FLD_HOST_DEBUG_STATE_OFFSET));
+        if (stat == BCM_FLD_HOST_START_CPU)
+            value |= ((1 << BCM_FLD_HOST_START_CPU_SHIFT) & BCM_FLD_HOST_START_CPU_MASK);
+        else if (stat == BCM_FLD_HOST_WRITE_DDR)
+            value |= ((1 << BCM_FLD_HOST_WRITE_DDR_SHIFT) & BCM_FLD_HOST_WRITE_DDR_MASK);
+        else
+            return BCM_ERR_PARM;
+    }
+    bcm_pci_write32(SRAM_ADDRESS(device,BCM_FLD_HOST_DEBUG_STATE_OFFSET), value);
+
+    return BCM_ERR_OK;
+}
+
+bcmos_errno bcm_fld_set_ras_mode_set(uint32_t device, uint32_t ras, uint32_t mode)
+{
+    uint32_t offset =  ras ? BCM_FLD_RAS_1_SETTINGS :BCM_FLD_RAS_0_SETTINGS;
+
+    bcm_pci_write32(SRAM_ADDRESS(device, offset), mode);
+
+    return BCM_ERR_OK;
+}
+
+bcmos_errno bcm_fld_set_host_event(uint32_t device, uint32_t event)
+{
+    if (!bcm68620_info)
+        return BCM_ERR_NORES;
+
+    if (device >= max_bcm68620_device)
+        return BCM_ERR_RANGE;
+
+    bcm_pci_write32(SRAM_ADDRESS(device, BCM_FLD_HOST_EVENT), event);
+
+    return BCM_ERR_OK;
+}
+
+bcmos_bool bcm_fld_test_queues_flag(uint32_t device)
+{
+    volatile uint32_t value;
+
+    if (!bcm68620_info)
+        return BCMOS_FALSE;
+
+    if (device >= max_bcm68620_device)
+        return BCMOS_FALSE;
+
+    value = bcm_pci_read32(SRAM_ADDRESS(device,BCM_FLD_CPU_SET_QUEUES_SIZE));
+    if (value & BCM_FLD_CPU_QUEUE_VALID_MASK)
+        return BCMOS_TRUE;
+
+    return BCMOS_FALSE;
+}
+
+bcmos_bool bcm_fld_regs_swap_needed(uint32_t device)
+{
+    uint32_t value;
+
+    value = *(volatile uint32_t *)(bcm68620_info[device].soc_regs_base + PCIE_REVISION_REGISTER_OFFSET);
+    if ((value & 0xffff) != 0x0302)
+        return BCMOS_TRUE;
+
+    return BCMOS_FALSE;
+}
+
+bcmos_bool bcm_fld_sram_swap_needed(uint32_t device)
+{
+    uint32_t value;
+    uint8_t charvalue;
+
+    value = 0xaabbccdd;
+    *(volatile uint32_t *)bcm68620_info[device].soc_sram_base = value;
+    charvalue = *(volatile uint8_t *)bcm68620_info[device].soc_sram_base;
+    if (charvalue != *(uint8_t *)&value)
+        return BCMOS_TRUE;
+
+    return BCMOS_FALSE;
+}
+
+bcmos_bool bcm_fld_ddr_swap_needed(uint32_t device)
+{
+    uint32_t value;
+    volatile uint32_t *address;
+    uint8_t charvalue;
+
+    value = 0xaabbccdd;
+    address = (uint32_t *)(bcm68620_info[device].soc_ddr_base + bcm68620_info[device].soc_crt_length);
+    *address = value;
+    charvalue = *address;
+    if (charvalue != *&value)
+        return BCMOS_TRUE;
+
+    return BCMOS_FALSE;
+}
+
+#ifdef TX_ENABLE_EVENT_TRACE
+bcmos_errno bcm_fld_set_event_trace(uint32_t device)
+{
+    if (!bcm68620_info)
+        return BCM_ERR_NORES;
+
+    if (device >= max_bcm68620_device)
+        return BCM_ERR_RANGE;
+
+    bcm_pci_write32(SRAM_ADDRESS(device,BCM_FLD_EVENT_TRACE_OFFSET), 0x1);
+
+    return BCM_ERR_OK;
+}
+bcmos_errno bcm_fld_clear_event_trace(uint32_t device)
+{
+    if (!bcm68620_info)
+        return BCM_ERR_NORES;
+
+    if (device >= max_bcm68620_device)
+        return BCM_ERR_RANGE;
+
+    bcm_pci_write32(SRAM_ADDRESS(device,BCM_FLD_EVENT_TRACE_OFFSET), 0x0);
+
+    return BCM_ERR_OK;
+}
+#endif
+#ifdef DMA_STUB
+bcmos_errno bcm_fld_set_device_bootrecord_flag(uint32_t device)
+{
+    volatile uint32_t value;
+
+    value = BCM_FLD_CPU_PRM_VALID_MASK;
+    bcm_pci_write32(SRAM_ADDRESS(device,BCM_FLD_CPU_BOOTREC_STATE_OFFSET), value);
+
+    return BCM_ERR_OK;
+}
+
+bcmos_errno bcm_fld_set_device_bootrecord(uint32_t device, uint32_t *opaque_data)
+{
+    uint32_t *addr, *temp;
+    int32_t i;
+
+    temp = opaque_data;
+    addr = SRAM_ADDRESS(device,BCM_FLD_CPU_BOOTRECORD_OFFSET);
+    for (i = 0; i < PCIE_OPAQUE_DATA_SIZE / 4; i++)
+    {
+        bcm_pci_write32(addr++,*temp++);
+    }
+
+    return BCM_ERR_OK;
+}
+#endif
+
+bcmos_errno bcm_fld_set_avs_cont(uint32_t device, uint32_t value)
+{
+    bcm_pci_write32(SRAM_ADDRESS(device, BCM_FLD_AVS_SETTINGS), value);
+
+    return BCM_ERR_OK;
+}
+
+void *bcm_fld_get_sw_error_table(uint32_t device, uint32_t *size)
+{
+    *size = BCM_FLD_SW_ERROR_TABLE_SIZE;
+    return SRAM_ADDRESS(device, BCM_FLD_SW_ERROR_TABLE);
+}
+
+uint32_t bcm_fld_ddr_test_result_get(uint32_t device, uint32_t word)
+{
+    return bcm_pci_read32(SRAM_ADDRESS(device, BCM_FLD_DDR_TEST_RESULTS + (word * COMM_WORD_SIZE)));
+}
+
+#ifdef __KERNEL__
+EXPORT_SYMBOL(bcm_fld_init);
+EXPORT_SYMBOL(bcm_fld_clear_comm_area);
+EXPORT_SYMBOL(bcm_fld_exit);
+EXPORT_SYMBOL(bcm_fld_register);
+EXPORT_SYMBOL(bcm_fld_unregister);
+EXPORT_SYMBOL(bcm_fld_get_device_status);
+EXPORT_SYMBOL(bcm_fld_get_device_loading_state);
+EXPORT_SYMBOL(bcm_fld_host_finish_write_ddr);
+EXPORT_SYMBOL(bcm_fld_get_logs);
+EXPORT_SYMBOL(bcm_fld_write);
+EXPORT_SYMBOL(bcm_fld_read);
+EXPORT_SYMBOL(bcm_fld_start_bootloader);
+EXPORT_SYMBOL(bcm_fld_is_bootloader_done);
+EXPORT_SYMBOL(bcm_fld_set_rings_size);
+EXPORT_SYMBOL(bcm_fld_get_device_bootrecord);
+EXPORT_SYMBOL(bcm_fld_test_device_bootrecord_flag);
+EXPORT_SYMBOL(bcm_fld_clear_device_bootrecord_flag);
+EXPORT_SYMBOL(bcm_fld_set_host_bootrecord_flag);
+EXPORT_SYMBOL(bcm_fld_test_host_bootrecord_flag);
+EXPORT_SYMBOL(bcm_fld_test_queues_flag);
+EXPORT_SYMBOL(bcm_fld_get_device_debug_status);
+EXPORT_SYMBOL(bcm_fld_get_host_debug_status);
+EXPORT_SYMBOL(bcm_fld_set_host_debug_status);
+EXPORT_SYMBOL(bcm_fld_set_ras_mode_set);
+EXPORT_SYMBOL(bcm_fld_set_host_event);
+EXPORT_SYMBOL(bcm_fld_get_exception_state);
+EXPORT_SYMBOL(bcm_fld_clear_exception_state);
+EXPORT_SYMBOL(bcm_fld_copy_exception_log);
+EXPORT_SYMBOL(bcm_fld_regs_swap_needed);
+EXPORT_SYMBOL(bcm_fld_sram_swap_needed);
+EXPORT_SYMBOL(bcm_fld_ddr_swap_needed);
+#ifdef TX_ENABLE_EVENT_TRACE
+EXPORT_SYMBOL(bcm_fld_set_event_trace);
+EXPORT_SYMBOL(bcm_fld_clear_event_trace);
+#endif
+EXPORT_SYMBOL(bcm_fld_set_avs_cont);
+EXPORT_SYMBOL(bcm_fld_get_sw_error_table);
+#endif
diff --git a/bcm68620_release/release/host_driver/fld/bcmolt_fld.h b/bcm68620_release/release/host_driver/fld/bcmolt_fld.h
new file mode 100644
index 0000000..f2297b2
--- /dev/null
+++ b/bcm68620_release/release/host_driver/fld/bcmolt_fld.h
@@ -0,0 +1,456 @@
+/*
+<:copyright-BRCM:2016:DUAL/GPL:standard
+
+   Broadcom Proprietary and Confidential.(c) 2016 Broadcom
+   All Rights Reserved
+
+Unless you and Broadcom execute a separate written software license
+agreement governing use of this software, this software is licensed
+to you under the terms of the GNU General Public License version 2
+(the "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php,
+with the following added to such license:
+
+   As a special exception, the copyright holders of this software give
+   you permission to link this software with independent modules, and
+   to copy and distribute the resulting executable under terms of your
+   choice, provided that you also meet, for each linked independent
+   module, the terms and conditions of the license of that module.
+   An independent module is a module which is not derived from this
+   software.  The special exception does not apply to any modifications
+   of the software.
+
+Not withstanding the above, under no circumstances may you combine
+this software in any way with any other Broadcom software provided
+under a license other than the GPL, without Broadcom's express prior
+written consent.
+
+:>
+ */
+
+#ifndef BCMOLT_FLD_H
+#define BCMOLT_FLD_H
+
+#include "bcmos_system.h"
+#include "bcmolt_model_types.h"
+#include "bcmolt_model_ids.h"
+#include "bcm_fld_common.h"
+
+/** \defgroup \fld_data_types Data Types
+ * \ingroup fld
+ * @{
+ */
+
+#define PCIE_REVISION_REGISTER_OFFSET       0x6406CU /* PCIE_PCIE_PCIE_0_PCIE_PCIE_0_MISC_REVISION    */
+
+typedef struct
+{
+    unsigned long   soc_regs_base;
+    unsigned long   soc_sram_base;
+    unsigned long   soc_ddr_base;
+    uint32_t        soc_ddr_length;     /* ddr window length */
+    uint32_t        soc_crt_length;     /* ddr used for load length */
+} bcm_fld_device_info;
+
+typedef struct
+{
+    uint32_t    os_entry_offset;
+    uint32_t    protocol_version;
+    uint32_t    state;
+    uint32_t    reason;
+} bcm_fld_device_stat;
+
+/**
+* \brief Initialize internal data base
+*
+*  allocate the array of pointers to info per device allocate
+*  and clear the info structure for every possible device
+*
+* \param[in] max_devices How many devices might be defined
+*
+* \return
+* 0 if successful, <0 if failed
+*/
+bcmos_errno bcm_fld_init(uint32_t max_devices);
+
+/**
+* \brief Initialize communication area
+*
+*  clear the communication area
+*
+* \param[in] device Identifies the device
+*
+*/
+void bcm_fld_clear_comm_area(uint32_t device);
+
+/**
+* \brief Release internal data base
+*
+* \return
+* 0 if successful, <0 if failed
+*/
+bcmos_errno bcm_fld_exit(void);
+
+/**
+* \brief Register a device to driver
+*
+*  store user's information about the device
+*
+* \param[in] device Identifies the device
+* \param[in] info Information
+*   - regs base address
+*   - sram base address
+*   - ddr base address
+*   - ddr window size
+*
+* \return
+* 0 if successful, <0 if failed
+*/
+bcmos_errno bcm_fld_register(uint32_t device, bcm_fld_device_info *info);
+
+/**
+* \brief Unregister a device from driver
+*
+*  remove the device from the internal db
+*
+* \param[in] device Identifies the device
+*
+* \return
+* 0 if successful, <0 if failed
+*/
+bcmos_errno bcm_fld_unregister(uint32_t device);
+
+/**
+* \brief Read from communication SoC debug information
+*
+* \param[in] device Identifies the device
+* \param[in] debug_state Information to be filled pointer
+*
+* \return
+* 0 if successful, <0 if failed
+*/
+bcmos_errno bcm_fld_get_device_status(uint32_t device, bcm_fld_device_stat *debug_state);
+
+/**
+* \brief Read from communication SoC status
+*
+* \param[in] device Identifies the device
+* \param[in] cpu_state Information to be filled pointer
+*
+* \return
+* 0 if successful, <0 if failed
+*/
+bcmos_errno bcm_fld_get_device_loading_state(uint32_t device, BCM_FLD_CPU_STATE *cpu_state);
+
+/**
+* \brief Write in communication area the finish writing DDR
+*        indicator
+*
+* \param[in] device Identifies the device
+* \param[in] os_entry_address Entry point for embedded
+*       application
+*
+* \return
+* 0 if successful, <0 if failed
+*/
+bcmos_errno bcm_fld_host_finish_write_ddr(uint32_t device, uint32_t os_entry_address);
+
+/**
+* \brief Read from communication the logs area
+*
+* \param[in] device Identifies the device
+* \param[out] log_area Pointer logger area
+* \param[out] length Length logger area
+*
+* \return
+* 0 if successful, <0 if failed
+*/
+bcmos_errno bcm_fld_get_logs(uint32_t device, char **log_area, int *length);
+
+/**
+* \brief Write the received buffer to memory according to offset
+*        and type
+*
+* \param[in] device Identifies the device
+* \param[in] buff Pointer to the buffer to be written
+* \param[in] buff_size Buffer size
+* \param[in] offset_in_image offset to write the buffer
+* \param[in] image_type Loading type, according to destination :
+*       SRAM or DDR
+*
+* \return
+* 0 if successful, <0 if failed
+*/
+bcmos_errno bcm_fld_write(uint32_t device, char *buff, uint32_t buff_size, uint32_t offset_in_image, bcmolt_device_image_type image_type);
+
+/**
+* \brief Read into received buffer from memory according to
+*        offset and type
+*
+* \param[in] device Identifies the device
+* \param[in] buff Pointer to the buffer to receive the content
+* \param[in] buff_size Buffer size
+* \param[in] offset_in_image offset to read into the buffer
+* \param[in] image_type Loading type, according to destination :
+*       SRAM or DDR
+*
+* \return
+* 0 if successful, <0 if failed
+*/
+bcmos_errno bcm_fld_read(uint32_t device, char *buff, uint32_t *buff_size, uint32_t offset_in_image, bcmolt_device_image_type image_type);
+
+/**
+* \brief Take soc cpu out of reset
+*
+* \param[in] device Identifies the device
+*
+* \return
+* 0 if successful, <0 if failed
+*/
+bcmos_errno bcm_fld_start_bootloader(uint32_t device, uint32_t test_ddr);
+
+/**
+* \brief Check if bootloader finished to run
+*
+* \param[in] device Identifies the device
+*
+* \return
+* BCMOS_TRUE if successful, BCMOS_FALSE if failed
+*/
+bcmos_bool bcm_fld_is_bootloader_done(uint32_t device);
+
+bcmos_bool bcm_fld_is_ddr_test_done(uint32_t device);
+
+/**
+* \brief Check if SoC finished synchronization process
+*
+* \param[in] device Identifies the device
+*
+* \return
+*/
+bcmos_bool bcm_fld_test_device_bootrecord(uint32_t device);
+
+/**
+* \brief Returns the bootrecord of the SoC
+*
+* \param[in] device Identifies the device
+* \param[in] opaque_data Pointer to information
+*   - physical address of the buffer descriptors ring
+*   - physical address of shadow buffer descriptors ring
+*   info_length MUST be modulo 4
+*
+* \return
+* 0 if successful, <0 if failed
+*/
+bcmos_errno bcm_fld_get_device_bootrecord(uint32_t device, uint32_t *opaque_data);
+
+/**
+* \brief Set bootrecord valid bit to be checked by the device
+*
+* \param[in] device Identifies the device
+* \return
+* 0 if successful, <0 if failed
+*/
+bcmos_errno bcm_fld_set_host_bootrecord_flag(uint32_t device);
+
+/**
+* \brief Check bootrecord valid bit set previously by the device
+*
+* \param[in] device Identifies the device
+* \return
+* 0 if successful, <0 if failed
+*/
+bcmos_bool bcm_fld_test_host_bootrecord_flag(uint32_t device);
+
+/**
+* \brief Clear bootrecord valid bit to be checked by the device
+*
+* \param[in] device Identifies the device
+* \return
+* 0 if successful, <0 if failed
+*/
+bcmos_errno bcm_fld_clear_device_bootrecord_flag(uint32_t device);
+
+/**
+* \brief Check bootrecord valid bit set previously by the device
+*
+* \param[in] device Identifies the device
+* \return
+* 0 if successful, <0 if failed
+*/
+bcmos_bool bcm_fld_test_device_bootrecord_flag(uint32_t device);
+
+/**
+* \brief Write the tx and rx queue sizes to communication area
+*   set queue validity bit for the device
+*
+* \param[in] device Identifies the device
+* \param[in] host_tx_size Queue size : is also the device rx
+*       queue size
+* \param[in] host_rx_size Queue size : is also the device tx
+*       queue size
+* \return
+* 0 if successful, <0 if failed
+*/
+bcmos_errno bcm_fld_set_rings_size(uint32_t device, uint32_t host_tx_size, uint32_t host_rx_size);
+
+/**
+* \brief set DDR RASconfiguration properties
+*
+* \param[in] device Identifies the device
+*
+* \param[in] ras  Identifies the ras number , can be 0 or 1
+*
+* \param[in] mode Identifies mode - disable 0, gpon 1, xgpon 2,
+*
+* \return
+* 0 if successful, <0 if failed
+*/
+bcmos_errno bcm_fld_set_ras_mode_set(uint32_t device, uint32_t ras, uint32_t mode);
+
+/**
+* \brief Notify device about an event that occurred on the host side
+*
+* \param[in] device Identifies the device
+*
+* \param[in] event  User defined event
+*
+* \return
+* 0 if successful, <0 if failed
+*/
+bcmos_errno bcm_fld_set_host_event(uint32_t device, uint32_t event);
+
+/**
+* \brief Check queues valid bit set previously by Host
+*
+* \param[in] device Identifies the device
+*
+* \return
+* FALSE if PRM_VALID bit is not set, TRUE if PRM_VALID bit is
+* set
+*/
+bcmos_bool bcm_fld_test_queues_flag(uint32_t device);
+
+/**
+* \brief Get the exception area state, set by the device exception
+*        handler
+*
+* \param[in] device Identifies the device
+* \param[out] state Pointer to exception state on cpu0 value
+* \param[out] state Pointer to exception state on cpu1 value
+*
+* \return
+* 0 if successful, <0 if failed
+*/
+
+bcmos_errno bcm_fld_get_exception_state(uint32_t device, uint32_t *state0, uint32_t *state1);
+
+/**
+* \brief Clear the exception area state
+*
+* \param[in] device Identifies the device
+* \param[in] cpuid Identifies the the device cpu
+*
+* \return
+* 0 if successful, <0 if failed
+*/
+bcmos_errno bcm_fld_clear_exception_state(uint32_t device, uint32_t cpuid);
+
+/**
+* \brief Fill buffer with the exception area content, set by
+*        the device exception handler
+*
+* \param[in] device Identifies the device
+* \param[in] cpuid Identifies the the device cpu
+* \param[out] buffer Pointer to be filled with the exception
+*       area content
+* \param[out] length Length of the buffer
+*
+* \return
+* 0 if successful, <0 if failed
+*/
+bcmos_errno bcm_fld_copy_exception_log(uint32_t device, uint32_t cpuid, char *buffer, int *length);
+
+#ifdef TX_ENABLE_EVENT_TRACE
+/**
+* \brief Set event trace flag to be read by embedded and start
+*        traceing
+*
+* \param[in] device Identifies the device
+*
+* \return
+* 0 if successful, <0 if failed
+*/
+bcmos_errno bcm_fld_set_event_trace(uint32_t device);
+
+/**
+* \brief Clear event trace flag to be read by embedded and stop
+*        traceing
+*
+* \param[in] device Identifies the device
+*
+* \return
+* 0 if successful, <0 if failed
+*/
+bcmos_errno bcm_fld_clear_event_trace(uint32_t device);
+#endif
+
+/**
+* \Debug states and functions
+*/
+typedef struct
+{
+    uint32_t    write_sram;
+    uint32_t    start_device;
+    uint32_t    write_ddr;
+    uint32_t    finish_ddr;
+} bcm_fld_host_debug_state;
+
+typedef enum
+{
+    BCM_FLD_HOST_NONE,
+    BCM_FLD_HOST_WRITE_SRAM,    /* set before load  image to SRAM */
+    BCM_FLD_HOST_START_CPU,     /* set before resume ARM */
+    BCM_FLD_HOST_WRITE_DDR      /* set before load  image to DDR */
+} BCM_FLD_HOST_DEBUG_VALUES;
+
+typedef struct
+{
+    uint32_t boot_from_sram_states;
+    uint32_t boot_from_sram_errors;
+    uint32_t boot_from_sram_exception;
+    uint32_t run_from_ddr_state;
+} bcm_fld_device_debug_state;
+
+/**
+* \brief Set and get debugging traceing from communication area
+*
+* \param[in] device Identifies the device
+* \param[in] info Pointer to information
+*
+* \return
+* 0 if successful, <0 if failed
+*/
+/* returns soc debug states */
+bcmos_errno bcm_fld_get_device_debug_status(uint32_t device, bcm_fld_device_debug_state *info);
+/* deal with host states - functional and debug */
+bcmos_errno bcm_fld_get_host_debug_status(uint32_t device, bcm_fld_host_debug_state *info);
+bcmos_errno bcm_fld_set_host_debug_status(uint32_t device, BCM_FLD_HOST_DEBUG_VALUES stat);
+/**
+* \brief Check if swap needed for the respective memory
+*
+* \param[in] device Identifies the device
+*
+* \return
+* true if swap needed, false if swap not needed
+*/
+bcmos_bool bcm_fld_regs_swap_needed(uint32_t device);
+bcmos_bool bcm_fld_sram_swap_needed(uint32_t device);
+bcmos_bool bcm_fld_ddr_swap_needed(uint32_t device);
+
+bcmos_errno bcm_fld_set_avs_cont(uint32_t device, uint32_t value);
+
+void *bcm_fld_get_sw_error_table(uint32_t device, uint32_t *size);
+uint32_t bcm_fld_ddr_test_result_get(uint32_t device, uint32_t word);
+
+#endif
+