| anjana_sreekumar@infosys.com | 991c206 | 2020-01-08 11:42:57 +0530 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2003-2018, Great Software Laboratory Pvt. Ltd. |
| 3 | * Copyright (c) 2017 Intel Corporation |
| 4 | * Copyright (c) 2019, Infosys Ltd. |
| 5 | * |
| 6 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 7 | * you may not use this file except in compliance with the License. |
| 8 | * You may obtain a copy of the License at |
| 9 | * |
| 10 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 11 | * |
| 12 | * Unless required by applicable law or agreed to in writing, software |
| 13 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 14 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 15 | * See the License for the specific language governing permissions and |
| 16 | * limitations under the License. |
| 17 | */ |
| 18 | |
| 19 | #ifndef __MESSAGE_QUEUES_H_ |
| 20 | #define __MESSAGE_QUEUES_H_ |
| 21 | |
| 22 | #define S1AP_Q_DIR "/tmp/s1ap" |
| 23 | #define MME_APP_Q_DIR "/tmp/mme-app" |
| 24 | #define S6A_Q_DIR "/tmp/s6a" |
| 25 | #define S11_Q_DIR "/tmp/s11" |
| 26 | |
| 27 | #define MME_TOTAL_HANDLERS 7 |
| 28 | |
| 29 | /** |
| 30 | Message queues used across MME, S1ap, S11, S6a |
| 31 | **/ |
| 32 | |
| 33 | |
| 34 | /********** S1AP READ/WRITE QUEUE *************/ |
| 35 | #define S1AP_READ_QUEUE "/tmp/s1ap/s1ap_read_Q" |
| 36 | #define S1AP_WRITE_QUEUE "/tmp/s1ap/s1ap_write_Q" |
| 37 | |
| 38 | /********** GTP READ/WRITE QUEUE *************/ |
| 39 | #define GTP_READ_QUEUE "/tmp/s11/gtp_read_Q" |
| 40 | #define GTP_WRITE_QUEUE "/tmp/s11/gtp_write_Q" |
| 41 | |
| 42 | /********** S6 READ/WRITE QUEUE *************/ |
| 43 | #define S6_READ_QUEUE "/tmp/s6a/s6_read_Q" |
| 44 | #define S6_WRITE_QUEUE "/tmp/s6a/s6_write_Q" |
| 45 | |
| 46 | #define S6A_REQ_STAGE1_QUEUE "/tmp/s6a/req_Q" |
| 47 | #define S1AP_AUTHREQ_STAGE2_QUEUE "/tmp/s1ap/authq_stage2_Q" |
| 48 | #define S1AP_SECREQ_STAGE3_QUEUE "/tmp/s1ap/secreq_stage3_Q" |
| 49 | #define S1AP_ESMREQ_STAGE4_QUEUE "/tmp/s1ap/esmreq_stage4_Q" |
| 50 | #define S11_CSREQ_STAGE5_QUEUE "/tmp/s11/CSreq_stage5_Q" |
| 51 | #define S1AP_ICSREQ_STAGE6_QUEUE "/tmp/s1ap/icsreq_stage6_Q" |
| 52 | #define S11_MBREQ_STAGE7_QUEUE "/tmp/s11/MBreq_stage7_Q" |
| 53 | #define S11_DTCHREQ_STAGE1_QUEUE "/tmp/mme-app/s11_dtchreq_stage1_Q" |
| 54 | #define S6A_DTCHREQ_STAGE1_QUEUE "/tmp/mme-app/s6a_dtchreq_stage1_Q" |
| 55 | #define S1AP_DTCHACCEPT_STAGE2_QUEUE "/tmp/mme-app/s1ap_dtchaccept_stage2_Q" |
| 56 | #define S6A_PURGE_STAGE2_QUEUE "/tmp/s6a/PURGE_Q" |
| 57 | |
| 58 | #endif /*__MESSAGE_QUEUES_H*/ |