Shad Ansari | 2f7f9be | 2017-06-07 13:34:53 -0700 | [diff] [blame^] | 1 | /* |
| 2 | <:copyright-BRCM:2016:DUAL/GPL:standard |
| 3 | |
| 4 | Broadcom Proprietary and Confidential.(c) 2016 Broadcom |
| 5 | All Rights Reserved |
| 6 | |
| 7 | Unless you and Broadcom execute a separate written software license |
| 8 | agreement governing use of this software, this software is licensed |
| 9 | to you under the terms of the GNU General Public License version 2 |
| 10 | (the "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php, |
| 11 | with the following added to such license: |
| 12 | |
| 13 | As a special exception, the copyright holders of this software give |
| 14 | you permission to link this software with independent modules, and |
| 15 | to copy and distribute the resulting executable under terms of your |
| 16 | choice, provided that you also meet, for each linked independent |
| 17 | module, the terms and conditions of the license of that module. |
| 18 | An independent module is a module which is not derived from this |
| 19 | software. The special exception does not apply to any modifications |
| 20 | of the software. |
| 21 | |
| 22 | Not withstanding the above, under no circumstances may you combine |
| 23 | this software in any way with any other Broadcom software provided |
| 24 | under a license other than the GPL, without Broadcom's express prior |
| 25 | written consent. |
| 26 | |
| 27 | :> |
| 28 | */ |
| 29 | |
| 30 | #ifndef BCM_FLD_COMMON_H |
| 31 | #define BCM_FLD_COMMON_H |
| 32 | |
| 33 | #define BCM_FLD_SRAM_SIZE 0x00010000 /* 64 KB */ |
| 34 | |
| 35 | /******************************/ |
| 36 | /* FLD communication area */ |
| 37 | /******************************/ |
| 38 | #define COMM_WORD_SIZE 4 /* 32 bit, 4 byte */ |
| 39 | #define BCM_FLD_COMMUNICATION_AREA_TOP BCM_FLD_SRAM_SIZE |
| 40 | |
| 41 | /* Please do not change PCIE_OPAQUE_DATA_SIZE define, MUST be same as used by pcie dma driver */ |
| 42 | #define PCIE_OPAQUE_DATA_SIZE (2*4) /* two pointers (BD and SBD) */ |
| 43 | |
| 44 | #define BOOTRECORD_RESERVED (2*COMM_WORD_SIZE) /* 4 words reserved for future needs */ |
| 45 | #define BCM_FLD_CPU_POSTMORTEM_BUF_SIZE 0x00001000 |
| 46 | |
| 47 | #define BCM_FLD_CPU_STATE_OFFSET (BCM_FLD_COMMUNICATION_AREA_TOP - COMM_WORD_SIZE) /* 0xfffc */ |
| 48 | #define BCM_FLD_HOST_STATE_OFFSET (BCM_FLD_CPU_STATE_OFFSET - COMM_WORD_SIZE) |
| 49 | #define BCM_FLD_CPU_DEBUG_STATE_OFFSET (BCM_FLD_HOST_STATE_OFFSET - COMM_WORD_SIZE) |
| 50 | #define BCM_FLD_HOST_DEBUG_STATE_OFFSET (BCM_FLD_CPU_DEBUG_STATE_OFFSET - COMM_WORD_SIZE) |
| 51 | #define BCM_FLD_CPU_BOOTREC_STATE_OFFSET (BCM_FLD_HOST_DEBUG_STATE_OFFSET - COMM_WORD_SIZE) |
| 52 | #define BCM_FLD_HOST_BOOTREC_STATE_OFFSET (BCM_FLD_CPU_BOOTREC_STATE_OFFSET - COMM_WORD_SIZE) |
| 53 | |
| 54 | #define BCM_FLD_CPU_RESET_REASON_OFFSET (BCM_FLD_HOST_BOOTREC_STATE_OFFSET - COMM_WORD_SIZE) |
| 55 | #define BCM_FLD_CPU_EXCEP_REASON_OFFSET (BCM_FLD_CPU_RESET_REASON_OFFSET - COMM_WORD_SIZE) |
| 56 | #define BCM_FLD_CPU_DDR_MEMC_STATE_OFFSET (BCM_FLD_CPU_EXCEP_REASON_OFFSET - COMM_WORD_SIZE) |
| 57 | #define BCM_FLD_RAS_0_DDR_MEMC_STATE_OFFSET (BCM_FLD_CPU_DDR_MEMC_STATE_OFFSET - COMM_WORD_SIZE) |
| 58 | #define BCM_FLD_RAS_1_DDR_MEMC_STATE_OFFSET (BCM_FLD_RAS_0_DDR_MEMC_STATE_OFFSET - COMM_WORD_SIZE) |
| 59 | |
| 60 | #define BCM_FLD_CPU_DDR_PHY_STATE_OFFSET (BCM_FLD_RAS_1_DDR_MEMC_STATE_OFFSET - COMM_WORD_SIZE) |
| 61 | #define BCM_FLD_RAS_0_DDR_PHY_STATE_OFFSET (BCM_FLD_CPU_DDR_PHY_STATE_OFFSET - 6*COMM_WORD_SIZE) |
| 62 | #define BCM_FLD_RAS_1_DDR_PHY_STATE_OFFSET (BCM_FLD_RAS_0_DDR_PHY_STATE_OFFSET - 6*COMM_WORD_SIZE) |
| 63 | #define BCM_FLD_BOOT_PROTOCOL_VERSION_OFFSET (BCM_FLD_RAS_1_DDR_PHY_STATE_OFFSET - 6*COMM_WORD_SIZE) |
| 64 | #define BCM_FLD_OS_ENTRY_OFFSET (BCM_FLD_BOOT_PROTOCOL_VERSION_OFFSET - COMM_WORD_SIZE) |
| 65 | #define BCM_FLD_CPU_SET_QUEUES_SIZE (BCM_FLD_OS_ENTRY_OFFSET - COMM_WORD_SIZE) |
| 66 | |
| 67 | /******************************/ |
| 68 | /* Boot-record area */ |
| 69 | /******************************/ |
| 70 | /* host write for SoC its rx queue size */ |
| 71 | #define BCM_FLD_HOST_RX_QUEUE_SIZE_OFFSET (BCM_FLD_CPU_SET_QUEUES_SIZE - COMM_WORD_SIZE) |
| 72 | #define BCM_FLD_CPU_RX_QUEUE_SIZE_OFFSET (BCM_FLD_HOST_RX_QUEUE_SIZE_OFFSET - COMM_WORD_SIZE) |
| 73 | |
| 74 | #define BCM_FLD_CPU_BOOTRECORD_OFFSET (BCM_FLD_CPU_RX_QUEUE_SIZE_OFFSET - BOOTRECORD_RESERVED) |
| 75 | |
| 76 | #define BCM_FLD_HOST_BOOTRECORD_OFFSET (BCM_FLD_CPU_BOOTRECORD_OFFSET - PCIE_OPAQUE_DATA_SIZE - BOOTRECORD_RESERVED ) |
| 77 | |
| 78 | #define BCM_FLD_CPU1_POSTMORTEM_STATE (BCM_FLD_HOST_BOOTRECORD_OFFSET - COMM_WORD_SIZE) |
| 79 | #define BCM_FLD_CPU0_POSTMORTEM_STATE (BCM_FLD_CPU1_POSTMORTEM_STATE - COMM_WORD_SIZE) |
| 80 | |
| 81 | #define BCM_FLD_RAS_0_SETTINGS (BCM_FLD_CPU0_POSTMORTEM_STATE - COMM_WORD_SIZE) |
| 82 | #define BCM_FLD_RAS_1_SETTINGS (BCM_FLD_RAS_0_SETTINGS - COMM_WORD_SIZE) |
| 83 | |
| 84 | #define BCM_RAS_DISABLE 0x0 |
| 85 | #define BCM_RAS_MODE_GPON 0x1 |
| 86 | #define BCM_RAS_MODE_XGPON 0x2 |
| 87 | |
| 88 | #define BCM_FLD_AVS_SETTINGS (BCM_FLD_RAS_1_SETTINGS - COMM_WORD_SIZE) |
| 89 | #define BCM_FLD_AVS_STOP 0x0 |
| 90 | #define BCM_FLD_AVS_CONT 0x1 |
| 91 | |
| 92 | #ifdef TX_ENABLE_EVENT_TRACE |
| 93 | #define BCM_FLD_EVENT_TRACE_OFFSET (BCM_FLD_AVS_SETTINGS - COMM_WORD_SIZE) |
| 94 | |
| 95 | /********************************************************************************* |
| 96 | PAY ATTENTION !!! BCM_FLD_COMMUNICATION_AREA_BASE must be equal first byte in the FLD |
| 97 | communication area therefore it should be equal to the last define above |
| 98 | *********************************************************************************/ |
| 99 | |
| 100 | #define BCM_FLD_COMMUNICATION_AREA_BASE BCM_FLD_EVENT_TRACE_OFFSET |
| 101 | #else |
| 102 | #define BCM_FLD_COMMUNICATION_AREA_BASE BCM_FLD_RAS_1_SETTINGS |
| 103 | #endif |
| 104 | #define BCM_FLD_COMMUNICATION_AREA_SIZE BCM_FLD_COMMUNICATION_AREA_TOP - BCM_FLD_COMMUNICATION_AREA_BASE |
| 105 | |
| 106 | /********************************************************************************* |
| 107 | PAY ATTENTION !!! POSTMORTEM_BUF_OFFSET must be outside the communication area |
| 108 | therefore it should be defined from BCM_FLD_COMMUNICATION_AREA_BASE |
| 109 | *********************************************************************************/ |
| 110 | |
| 111 | #define BCM_FLD_CPU1_POSTMORTEM_BUF_OFFSET (BCM_FLD_COMMUNICATION_AREA_BASE - BCM_FLD_CPU_POSTMORTEM_BUF_SIZE) |
| 112 | #define BCM_FLD_CPU0_POSTMORTEM_BUF_OFFSET (BCM_FLD_CPU1_POSTMORTEM_BUF_OFFSET - BCM_FLD_CPU_POSTMORTEM_BUF_SIZE) |
| 113 | #define BCM_FLD_HOST_EVENT (BCM_FLD_CPU0_POSTMORTEM_BUF_OFFSET - COMM_WORD_SIZE) |
| 114 | |
| 115 | #define BCM_FLD_DDR_TEST_RESULTS_SIZE (3 * COMM_WORD_SIZE) /* CPU + RAS 0 + RAS 1 */ |
| 116 | #define BCM_FLD_DDR_TEST_RESULTS (BCM_FLD_HOST_EVENT - BCM_FLD_DDR_TEST_RESULTS_SIZE) |
| 117 | |
| 118 | /* SW Error table */ |
| 119 | #define BCM_FLD_SW_ERROR_TABLE_SIZE (1171 * COMM_WORD_SIZE) |
| 120 | #define BCM_FLD_SW_ERROR_TABLE (BCM_FLD_DDR_TEST_RESULTS - BCM_FLD_SW_ERROR_TABLE_SIZE) |
| 121 | |
| 122 | /* logger will NOT overwrite other fields */ |
| 123 | #define BCM_FLD_LOGGER_TOP BCM_FLD_SW_ERROR_TABLE |
| 124 | #define BCM_FLD_LOGGER_BASE 0 /* logger will overwrite the bootloader */ |
| 125 | |
| 126 | /* BCM68620 (Maple) functional states */ |
| 127 | #define BCM_FLD_CPU_FINISH_BOOTLOADER_SHIFT 0 |
| 128 | #define BCM_FLD_CPU_FINISH_BOOTLOADER_MASK (0x1 << BCM_FLD_CPU_FINISH_BOOTLOADER_SHIFT) |
| 129 | |
| 130 | #define BCM_FLD_CPU_READY_SHIFT 1 |
| 131 | #define BCM_FLD_CPU_READY_MASK (0x1 << BCM_FLD_CPU_READY_SHIFT) |
| 132 | |
| 133 | #define BCM_FLD_DDR_TEST_DONE_SHIFT 2 |
| 134 | #define BCM_FLD_DDR_TEST_DONE_MASK (0x1 << BCM_FLD_DDR_TEST_DONE_SHIFT) |
| 135 | |
| 136 | /* BCM68620 (Host) functional states */ |
| 137 | #define BCM_FLD_HOST_FINISH_WRITE_DDR_SHIFT 0 |
| 138 | #define BCM_FLD_HOST_FINISH_WRITE_DDR_MASK (0x1 << BCM_FLD_HOST_FINISH_WRITE_DDR_SHIFT) |
| 139 | |
| 140 | #define BCM_FLD_HOST_RUN_CPU_DDR_TEST_SHIFT 1 |
| 141 | #define BCM_FLD_HOST_RUN_CPU_DDR_TEST_MASK (0x1 << BCM_FLD_HOST_RUN_CPU_DDR_TEST_SHIFT) |
| 142 | |
| 143 | #define BCM_FLD_HOST_RUN_RAS_0_TEST_SHIFT 2 |
| 144 | #define BCM_FLD_HOST_RUN_RAS_0_TEST_MASK (0x1 << BCM_FLD_HOST_RUN_RAS_0_TEST_SHIFT) |
| 145 | |
| 146 | #define BCM_FLD_HOST_RUN_RAS_1_TEST_SHIFT 3 |
| 147 | #define BCM_FLD_HOST_RUN_RAS_1_TEST_MASK (0x1 << BCM_FLD_HOST_RUN_RAS_1_TEST_SHIFT) |
| 148 | |
| 149 | /* host bootrecord states */ |
| 150 | #define BCM_FLD_HOST_PRM_VALID_SHIFT 0 |
| 151 | #define BCM_FLD_HOST_PRM_VALID_MASK (0x1 << BCM_FLD_HOST_PRM_VALID_SHIFT) |
| 152 | |
| 153 | /* device bootrecord states */ |
| 154 | #define BCM_FLD_CPU_PRM_VALID_SHIFT 0 |
| 155 | #define BCM_FLD_CPU_PRM_VALID_MASK (0x1 << BCM_FLD_CPU_PRM_VALID_SHIFT) |
| 156 | |
| 157 | /* queue validity flag */ |
| 158 | #define BCM_FLD_CPU_QUEUE_VALID_SHIFT 0 |
| 159 | #define BCM_FLD_CPU_QUEUE_VALID_MASK (0x1 << BCM_FLD_CPU_QUEUE_VALID_SHIFT) |
| 160 | |
| 161 | /* CPU debug states */ |
| 162 | #define CPU_DEBUG_BOOT_FLASH (1<<0) |
| 163 | #define CPU_DEBUG_RUN__FROM_SRAM (1<<1) |
| 164 | #define CPU_DEBUG_LUT_DONE (1<<2) |
| 165 | #define CPU_DEBUG_B15_CFG_DONE (1<<3) |
| 166 | #define CPU_DEBUG_UART_INIT_DONE (1<<4) |
| 167 | #define CPU_DEBUG_CLEAR_BSS_DONE (1<<5) |
| 168 | #define CPU_DEBUG_RUN_C (1<<6) |
| 169 | #define CPU_DEBUG_FLASH_READ_FAILED (1<<7) |
| 170 | #define CPU_DEBUG_OS_FAILED (1<<8) |
| 171 | |
| 172 | /* CPU exception reason */ |
| 173 | #define CPU_EXCEP_UNDEF_INSTR (1<<0) |
| 174 | #define CPU_EXCEP_SW_INTR (1<<1) |
| 175 | #define CPU_EXCEP_PREFETCH_ABORT (1<<2) |
| 176 | #define CPU_EXCEP_DATA_ABORT (1<<3) |
| 177 | #define CPU_EXCEP_IRQ (1<<4) |
| 178 | #define CPU_EXCEP_FIQ (1<<5) |
| 179 | |
| 180 | #ifndef __ASSEMBLER__ |
| 181 | /* SoC states values */ |
| 182 | typedef enum |
| 183 | { |
| 184 | BCM_FLD_CPU_STATE_UNKNOWN, |
| 185 | BCM_FLD_SRAM_BOOT_DONE, |
| 186 | BCM_FLD_BOOT_FROM_DDR, |
| 187 | BCM_FLD_RUN_FROM_DDR, |
| 188 | BCM_FLD_CPU_READY, |
| 189 | BCM_FLD_HOST_READY, |
| 190 | BCM_FLD_CPU_FINISH_BOOTLOADER |
| 191 | } BCM_FLD_CPU_STATE; |
| 192 | |
| 193 | /* SoC reset values */ |
| 194 | typedef enum |
| 195 | { |
| 196 | BCM_FLD_CPU_RESET_UNKNOWN |
| 197 | } BCM_FLD_CPU_RESET_REASON; |
| 198 | |
| 199 | typedef enum |
| 200 | { |
| 201 | BCM_FLD_RAS_MODE_NOT_CONFIGURED, |
| 202 | BCM_FLD_RAS_MODE_GPON, |
| 203 | BCM_FLD_RAS_MODE_XGPON, |
| 204 | BCM_FLD_RAS_MODE_XGS_NGPON2, |
| 205 | } BCM_FLD_RSM_MODE; |
| 206 | |
| 207 | typedef struct |
| 208 | { |
| 209 | unsigned int magic; |
| 210 | unsigned int msg_len; |
| 211 | char msg[1]; |
| 212 | } BCM_FLD_POSTMORTEM_LOG; |
| 213 | #endif |
| 214 | |
| 215 | #define BCM_FLD_POSTMORTEM_LOG_MAGIC 0xFEEDBACC |
| 216 | |
| 217 | /* device_debug_states */ |
| 218 | #define BCM_FLD_CPU_BOOT_FROM_SRAM_STATES_SHIFT 0 |
| 219 | #define BCM_FLD_CPU_BOOT_FROM_SRAM_STATES_MASK 0x000000ffU |
| 220 | #define BCM_FLD_CPU_BOOT_FROM_SRAM_ERRORS_SHIFT 8 |
| 221 | #define BCM_FLD_CPU_BOOT_FROM_SRAM_ERRORS_MASK 0x0000ff00U |
| 222 | #define BCM_FLD_CPU_BOOT_FROM_SRAM_EXCEPTION_SHIFT 16 |
| 223 | #define BCM_FLD_CPU_BOOT_FROM_SRAM_EXCEPTION_MASK 0x00ff0000U |
| 224 | #define BCM_FLD_CPU_RUN_FROM_DDR_STATES_SHIFT 24 |
| 225 | #define BCM_FLD_CPU_RUN_FROM_DDR_STATES_MASK 0xff000000U |
| 226 | /* host_debug_states */ |
| 227 | #define BCM_FLD_HOST_WRITE_SRAM_SHIFT 0 |
| 228 | #define BCM_FLD_HOST_WRITE_SRAM_MASK 0x00000001U |
| 229 | #define BCM_FLD_HOST_START_CPU_SHIFT 1 |
| 230 | #define BCM_FLD_HOST_START_CPU_MASK 0x00000002U |
| 231 | #define BCM_FLD_HOST_WRITE_DDR_SHIFT 2 |
| 232 | #define BCM_FLD_HOST_WRITE_DDR_MASK 0x00000004U |
| 233 | |
| 234 | #define CPU_2_PCIE_MEM_WIN0_BASE 0x90000000 |
| 235 | #define CPU_2_PCIE_MEM_WIN0_SIZE 0x00100000 |
| 236 | #define MAX_PMC_SIZE 0x8000 |
| 237 | |
| 238 | #ifdef TX_ENABLE_EVENT_TRACE |
| 239 | #define EVENT_BUFFER_SIZE 0x00600000 /* 6 Mbyte */ |
| 240 | /* leave 1 Mbyte gap between windows */ |
| 241 | #define CPU_2_PCIE_MEM_WIN1_BASE CPU_2_PCIE_MEM_WIN0_BASE + CPU_2_PCIE_MEM_WIN0_SIZE + 0x100000 |
| 242 | #define CPU_2_PCIE_MEM_WIN1_SIZE EVENT_BUFFER_SIZE |
| 243 | #endif |
| 244 | |
| 245 | #endif |