Shad Ansari | 2f7f9be | 2017-06-07 13:34:53 -0700 | [diff] [blame] | 1 | # |
| 2 | # $Id: config-sand.bcm,v 1.140 2013/09/22 14:29:47 tomerma Exp $ |
| 3 | # |
| 4 | # $Copyright: (c) 2011 Broadcom Corporation |
| 5 | # All Rights Reserved.$ |
| 6 | |
| 7 | ######################################### |
| 8 | ##cfg for BCM88640 (PetraB) and BCM88650 (Arad) |
| 9 | ######################################### |
| 10 | |
| 11 | ## temporary suppressing unknown soc properties warnings - till adding them unknown to property.h/propgen |
| 12 | ## (need to be the first soc property in the file). |
| 13 | suppress_unknown_prop_warnings=1 |
| 14 | |
| 15 | ## Multi device system (Negev): 2 devices, fabric mode is FE, mod id is slot id |
| 16 | ## (Top line card is 0, button is 1). |
| 17 | #diag_chassis=1 |
| 18 | |
| 19 | ## Disable diag init application. Should be used if one wants to run his own |
| 20 | ## application instead of the diag init example |
| 21 | #diag_disable=1 |
| 22 | |
| 23 | ## Skip cosq configuration in diag_init |
| 24 | #diag_cosq_disable=1 |
| 25 | |
| 26 | ######################################### |
| 27 | ##cfg for BCM88650 - Arad |
| 28 | ######################################### |
| 29 | |
| 30 | ### Device configuration ### |
| 31 | |
| 32 | ## Activate Emulation partial init. Values: 0 - Normal, 1 - Emulation .Default: 0x0. |
| 33 | diag_emulator_partial_init.BCM88650=0 |
| 34 | |
| 35 | ## General |
| 36 | # Set the FAP Device mode |
| 37 | # Options: PP / TM / TDM_OPTIMIZED / TDM_STANDARD |
| 38 | fap_device_mode.BCM88650=PP |
| 39 | |
| 40 | ## Credit worth size (Bytes) |
| 41 | credit_size.BCM88650=1024 |
| 42 | |
| 43 | ## Clock configurations |
| 44 | # Core clock speed (MHz). Default: 600 MHz |
| 45 | core_clock_speed_khz.BCM88650=600000 |
| 46 | # System reference clock (MHz). Default: 600 MHz |
| 47 | system_ref_core_clock_khz.BCM88650=600000 |
| 48 | |
| 49 | ### Network Interface configuration ### |
| 50 | ## Use of the ucode_port_<Local-Port-Id>=<Interface-type>[<Interface-Id>][.<Channel-Id>] |
| 51 | ## Local port range: 0 - 255. |
| 52 | ## Interface types: XAUI/RXAUI/SGMII/ILKN/10GBase-R/XLGE/CGE/CPU |
| 53 | |
| 54 | # Map bcm local port to CPU[.channel] interfaces |
| 55 | ucode_port_180.BCM88650=CPU.0 |
| 56 | |
| 57 | pon_application_support_enabled_0.BCM88650=TRUE |
| 58 | pon_application_support_enabled_1.BCM88650=TRUE |
| 59 | pon_application_support_enabled_2.BCM88650=TRUE |
| 60 | pon_application_support_enabled_3.BCM88650=TRUE |
| 61 | #pon_application_support_enabled_4.BCM88650=TRUE |
| 62 | #pon_application_support_enabled_5.BCM88650=TRUE |
| 63 | #pon_application_support_enabled_6.BCM88650=TRUE |
| 64 | #pon_application_support_enabled_7.BCM88650=TRUE |
| 65 | |
| 66 | vlan_match_criteria_mode=PON_PCP_ETHERTYPE |
| 67 | |
| 68 | #Firmware mode: |
| 69 | # 0=DEFAULT |
| 70 | # 1=SFP_OPT_SR4 - optical short range |
| 71 | # 2=SFP_DAC - direct attach copper |
| 72 | # 3=XLAUI - 40G XLAUI mode |
| 73 | # 4=FORCE_OSDFE - force over sample digital feedback equalization |
| 74 | # 5=FORCE_BRDFE - force baud rate digital feedback equalization |
| 75 | # 6=SW_CL72 - software cl72 with AN on |
| 76 | # 7=CL72_WITHOUT_AN - cl72 without AN |
| 77 | #For Negev2 chassis enable DFE is recommended |
| 78 | |
| 79 | serdes_if_type=1024 |
| 80 | |
| 81 | #serdes_firmware_mode.BCM88650=3 |
| 82 | serdes_firmware_mode_il.BCM88650=4 |
| 83 | serdes_firmware_mode_sfi.BCM88650=0 |
| 84 | |
| 85 | # |
| 86 | # Serdes firmware mode for Channelized PON interfaces |
| 87 | # |
| 88 | #serdes_firmware_mode_xe0.BCM88650=0 |
| 89 | #serdes_firmware_mode_xe1.BCM88650=0 |
| 90 | #serdes_firmware_mode_xe2.BCM88650=0 |
| 91 | #serdes_firmware_mode_xe3.BCM88650=0 |
| 92 | #serdes_firmware_mode_xe4.BCM88650=0 |
| 93 | #serdes_firmware_mode_xe5.BCM88650=0 |
| 94 | #serdes_firmware_mode_xe6.BCM88650=0 |
| 95 | #serdes_firmware_mode_xe7.BCM88650=0 |
| 96 | #serdes_firmware_mode_xe8.BCM88650=0 |
| 97 | #serdes_firmware_mode_xe9.BCM88650=0 |
| 98 | #serdes_firmware_mode_xe10.BCM88650=0 |
| 99 | #serdes_firmware_mode_xe11.BCM88650=0 |
| 100 | #serdes_firmware_mode_xe12.BCM88650=0 |
| 101 | #serdes_firmware_mode_xe13.BCM88650=0 |
| 102 | #serdes_firmware_mode_xe14.BCM88650=0 |
| 103 | #serdes_firmware_mode_xe15.BCM88650=0 |
| 104 | |
| 105 | # |
| 106 | # Serdes firmware mode for NNI interfaces |
| 107 | # |
| 108 | serdes_firmware_mode_xe128.BCM88650=2 |
| 109 | serdes_firmware_mode_xe129.BCM88650=2 |
| 110 | serdes_firmware_mode_xe130.BCM88650=2 |
| 111 | serdes_firmware_mode_xe131.BCM88650=2 |
| 112 | serdes_firmware_mode_xe0.BCM88650=2 |
| 113 | serdes_firmware_mode_xe1.BCM88650=2 |
| 114 | serdes_firmware_mode_xe2.BCM88650=2 |
| 115 | serdes_firmware_mode_xe3.BCM88650=2 |
| 116 | |
| 117 | # |
| 118 | # Set the speed for the PON-side ports (connected to Pioneer) to 12.5G |
| 119 | # |
| 120 | #port_init_speed_xe0.BCM88650=12500 |
| 121 | #port_init_speed_xe1.BCM88650=12500 |
| 122 | #IL# change xe3, xe2 speed to 2.5G and 1G |
| 123 | port_init_speed_xe2.BCM88650=2500 |
| 124 | port_init_speed_xe3.BCM88650=1000 |
| 125 | #port_init_speed_xe4.BCM88650=12500 |
| 126 | #port_init_speed_xe5.BCM88650=12500 |
| 127 | #port_init_speed_xe6.BCM88650=12500 |
| 128 | #port_init_speed_xe7.BCM88650=12500 |
| 129 | #port_init_speed_xe8.BCM88650=12500 |
| 130 | #port_init_speed_xe9.BCM88650=12500 |
| 131 | #port_init_speed_xe10.BCM88650=12500 |
| 132 | #port_init_speed_xe11.BCM88650=12500 |
| 133 | #port_init_speed_xe12.BCM88650=12500 |
| 134 | #port_init_speed_xe13.BCM88650=12500 |
| 135 | #port_init_speed_xe14.BCM88650=12500 |
| 136 | #port_init_speed_xe15.BCM88650=12500 |
| 137 | |
| 138 | # |
| 139 | # Set the number of priorities for the PON-side ports (connected to |
| 140 | # Pioneer) to '2'. |
| 141 | # |
| 142 | port_priorities_xe0.BCM88650=2 |
| 143 | port_priorities_xe1.BCM88650=2 |
| 144 | port_priorities_xe2.BCM88650=2 |
| 145 | port_priorities_xe3.BCM88650=2 |
| 146 | #port_priorities_xe4.BCM88650=2 |
| 147 | #port_priorities_xe5.BCM88650=2 |
| 148 | #port_priorities_xe6.BCM88650=2 |
| 149 | #port_priorities_xe7.BCM88650=2 |
| 150 | #port_priorities_xe8.BCM88650=2 |
| 151 | #port_priorities_xe9.BCM88650=2 |
| 152 | #port_priorities_xe10.BCM88650=2 |
| 153 | #port_priorities_xe11.BCM88650=2 |
| 154 | #port_priorities_xe12.BCM88650=2 |
| 155 | #port_priorities_xe13.BCM88650=2 |
| 156 | #port_priorities_xe14.BCM88650=2 |
| 157 | #port_priorities_xe15.BCM88650=2 |
| 158 | |
| 159 | # |
| 160 | # Map bcm local port to Network-Interface[.channel] interfaces |
| 161 | # |
| 162 | # PON Interfaces |
| 163 | # |
| 164 | |
| 165 | # |
| 166 | # Non-channelized PON Interfaces |
| 167 | # |
| 168 | # Uncomment the following if using non-channelized PON interfaces with |
| 169 | # Pioneer. |
| 170 | # |
| 171 | #ucode_port_0.BCM88650=10GBase-R8 |
| 172 | #ucode_port_1.BCM88650=10GBase-R9 |
| 173 | #ucode_port_2.BCM88650=10GBase-R10 |
| 174 | #ucode_port_3.BCM88650=10GBase-R11 |
| 175 | #ucode_port_4.BCM88650=10GBase-R12 |
| 176 | #ucode_port_5.BCM88650=10GBase-R13 |
| 177 | #ucode_port_6.BCM88650=10GBase-R14 |
| 178 | #ucode_port_7.BCM88650=10GBase-R15 |
| 179 | |
| 180 | # |
| 181 | # Channelized PON Interfaces |
| 182 | # |
| 183 | # Define virtual ports for the 10G Channels |
| 184 | # |
| 185 | #ucode_port_0.BCM88650=10GBase-R8.0 |
| 186 | #ucode_port_1.BCM88650=10GBase-R9.0 |
| 187 | #ucode_port_2.BCM88650=10GBase-R10.0 |
| 188 | #ucode_port_3.BCM88650=10GBase-R11.0 |
| 189 | #ucode_port_4.BCM88650=10GBase-R12.0 |
| 190 | #ucode_port_5.BCM88650=10GBase-R13.0 |
| 191 | #ucode_port_6.BCM88650=10GBase-R14.0 |
| 192 | #ucode_port_7.BCM88650=10GBase-R15.0 |
| 193 | |
| 194 | # |
| 195 | # Define virtual ports for the 1G Channels |
| 196 | # |
| 197 | #ucode_port_8.BCM88650=10GBase-R8.1 |
| 198 | #ucode_port_9.BCM88650=10GBase-R9.1 |
| 199 | #ucode_port_10.BCM88650=10GBase-R10.1 |
| 200 | #ucode_port_11.BCM88650=10GBase-R11.1 |
| 201 | #ucode_port_12.BCM88650=10GBase-R12.1 |
| 202 | #ucode_port_13.BCM88650=10GBase-R13.1 |
| 203 | #ucode_port_14.BCM88650=10GBase-R14.1 |
| 204 | #ucode_port_15.BCM88650=10GBase-R15.1 |
| 205 | |
| 206 | # |
| 207 | # NNI Interfaces |
| 208 | # |
| 209 | ucode_port_128.BCM88650=10GBase-R0 |
| 210 | ucode_port_129.BCM88650=10GBase-R1 |
| 211 | ucode_port_130.BCM88650=10GBase-R2 |
| 212 | ucode_port_131.BCM88650=10GBase-R3 |
| 213 | ucode_port_0.BCM88650=10GBase-R4 |
| 214 | ucode_port_1.BCM88650=10GBase-R5 |
| 215 | ucode_port_2.BCM88650=10GBase-R6 |
| 216 | ucode_port_3.BCM88650=10GBase-R7 |
| 217 | |
| 218 | #ucode_port_200.BCM88650=CPU.1 |
| 219 | #ucode_port_201.BCM88650=CPU.2 |
| 220 | #ucode_port_202.BCM88650=CPU.3 |
| 221 | #ucode_port_203.BCM88650=CPU.4 |
| 222 | |
| 223 | #40G |
| 224 | #ucode_port_1.BCM88650=XLGE0 |
| 225 | #ucode_port_2.BCM88650=XLGE1 |
| 226 | #ucode_port_3.BCM88650=XLGE2 |
| 227 | #ucode_port_4.BCM88650=XLGE3 |
| 228 | #ucode_port_5.BCM88650=XLGE4 |
| 229 | #ucode_port_6.BCM88650=XLGE5 |
| 230 | #ucode_port_7.BCM88650=XLGE6 |
| 231 | |
| 232 | #ILKN configuration - basic config |
| 233 | #ucode_port_31.BCM88650=ILKN0 |
| 234 | #ucode_port_32.BCM88650=ILKN1 |
| 235 | #ilkn_num_lanes_0.BCM88650=12 |
| 236 | #ilkn_num_lanes_1.BCM88650=12 |
| 237 | #port_init_speed_il.BCM88650=10312 |
| 238 | |
| 239 | |
| 240 | #ILKN per port channel stat |
| 241 | #ilkn_counters_mode.BCM88650=PACKET_PER_CHANNEL |
| 242 | |
| 243 | #ILKN configuration - advanced |
| 244 | #ilkn_metaframe_sync_period=2048 |
| 245 | # Enable\Disable ILKN status message sent through an out-of-band interface. |
| 246 | # ilkn_interface_status_oob_ignore.BCM88650=1 |
| 247 | |
| 248 | ##ILKN retransmit |
| 249 | #ilkn_retransmit_enable_rx.BCM88650=1 |
| 250 | #ilkn_retransmit_enable_tx.BCM88650=1 |
| 251 | #ilkn_retransmit_buffer_size.BCM88650=250 |
| 252 | #ilkn_retransmit_num_requests_resent.BCM88650=15 |
| 253 | #ilkn_retransmit_num_sn_repetitions_tx.BCM88650=1 |
| 254 | #ilkn_retransmit_num_sn_repetitions_rx.BCM88650=1 |
| 255 | #ilkn_retransmit_rx_timeout_words.BCM88650=3800 |
| 256 | #ilkn_retransmit_rx_timeout_sn.BCM88650=250 |
| 257 | #ilkn_retransmit_rx_ignore.BCM88650=80 |
| 258 | #ilkn_retransmit_rx_reset_when_error_enable.BCM88650=1 |
| 259 | #ilkn_retransmit_rx_watchdog.BCM88650=0 |
| 260 | #ilkn_retransmit_rx_reset_when_alligned_error_enable.BCM88650=1 |
| 261 | #ilkn_retransmit_rx_reset_when_retry_error_enable.BCM88650=1 |
| 262 | #ilkn_retransmit_rx_reset_when_wrap_after_disc_error_enable.BCM88650=1 |
| 263 | #ilkn_retransmit_rx_reset_when_wrap_before_disc_error_enable.BCM88650=0 |
| 264 | #ilkn_retransmit_rx_reset_when_timout_error_enable.BCM88650=0 |
| 265 | #ilkn_retransmit_tx_wait_for_seq_num_change_enable.BCM88650=1 |
| 266 | #ilkn_retransmit_tx_ignore_requests_when_fifo_almost_empty.BCM88650=1 |
| 267 | |
| 268 | #ucode_port_40.BCM88650=RCY.0 |
| 269 | #ucode_port_41.BCM88650=RCY.1 |
| 270 | #ucode_port_42.BCM88650=RCY.2 |
| 271 | |
| 272 | ## CAUI Configuration |
| 273 | #ucode_port_41.BCM88650=CGE0 |
| 274 | #ucode_port_42.BCM88650=CGE1 |
| 275 | caui_num_lanes_0.BCM88650=10 |
| 276 | caui_num_lanes_1.BCM88650=10 |
| 277 | #Required for working IXIA 100G port: |
| 278 | mld_lane_swap_lane20_ce.BCM88650=0 |
| 279 | mld_lane_swap_lane21_ce.BCM88650=1 |
| 280 | mld_lane_swap_lane0_ce.BCM88650=20 |
| 281 | mld_lane_swap_lane1_ce.BCM88650=21 |
| 282 | |
| 283 | # This configures the lane polarity |
| 284 | pb_serdes_lane_swap_polarity_tx_phy1.BCM88650=1 |
| 285 | pb_serdes_lane_swap_polarity_tx_phy2.BCM88650=0 |
| 286 | pb_serdes_lane_swap_polarity_tx_phy3.BCM88650=0 |
| 287 | pb_serdes_lane_swap_polarity_tx_phy4.BCM88650=0 |
| 288 | pb_serdes_lane_swap_polarity_tx_phy5.BCM88650=1 |
| 289 | pb_serdes_lane_swap_polarity_tx_phy6.BCM88650=0 |
| 290 | pb_serdes_lane_swap_polarity_tx_phy7.BCM88650=0 |
| 291 | pb_serdes_lane_swap_polarity_tx_phy8.BCM88650=0 |
| 292 | pb_serdes_lane_swap_polarity_tx_phy9.BCM88650=0 |
| 293 | pb_serdes_lane_swap_polarity_tx_phy10.BCM88650=0 |
| 294 | pb_serdes_lane_swap_polarity_tx_phy11.BCM88650=0 |
| 295 | pb_serdes_lane_swap_polarity_tx_phy12.BCM88650=0 |
| 296 | pb_serdes_lane_swap_polarity_tx_phy13.BCM88650=0 |
| 297 | pb_serdes_lane_swap_polarity_tx_phy14.BCM88650=0 |
| 298 | pb_serdes_lane_swap_polarity_tx_phy15.BCM88650=0 |
| 299 | pb_serdes_lane_swap_polarity_tx_phy16.BCM88650=0 |
| 300 | pb_serdes_lane_swap_polarity_tx_phy17.BCM88650=0 |
| 301 | pb_serdes_lane_swap_polarity_tx_phy18.BCM88650=0 |
| 302 | pb_serdes_lane_swap_polarity_tx_phy19.BCM88650=0 |
| 303 | pb_serdes_lane_swap_polarity_tx_phy20.BCM88650=0 |
| 304 | pb_serdes_lane_swap_polarity_tx_phy21.BCM88650=0 |
| 305 | pb_serdes_lane_swap_polarity_tx_phy22.BCM88650=0 |
| 306 | pb_serdes_lane_swap_polarity_tx_phy23.BCM88650=0 |
| 307 | pb_serdes_lane_swap_polarity_tx_phy24.BCM88650=0 |
| 308 | pb_serdes_lane_swap_polarity_tx_phy25.BCM88650=0 |
| 309 | pb_serdes_lane_swap_polarity_tx_phy26.BCM88650=0 |
| 310 | pb_serdes_lane_swap_polarity_tx_phy27.BCM88650=0 |
| 311 | pb_serdes_lane_swap_polarity_tx_phy28.BCM88650=0 |
| 312 | |
| 313 | pb_serdes_lane_swap_polarity_rx_phy1.BCM88650=0 |
| 314 | pb_serdes_lane_swap_polarity_rx_phy2.BCM88650=0 |
| 315 | pb_serdes_lane_swap_polarity_rx_phy3.BCM88650=0 |
| 316 | pb_serdes_lane_swap_polarity_rx_phy4.BCM88650=0 |
| 317 | pb_serdes_lane_swap_polarity_rx_phy5.BCM88650=0 |
| 318 | pb_serdes_lane_swap_polarity_rx_phy6.BCM88650=0 |
| 319 | pb_serdes_lane_swap_polarity_rx_phy7.BCM88650=0 |
| 320 | pb_serdes_lane_swap_polarity_rx_phy8.BCM88650=0 |
| 321 | pb_serdes_lane_swap_polarity_rx_phy9.BCM88650=0 |
| 322 | pb_serdes_lane_swap_polarity_rx_phy10.BCM88650=0 |
| 323 | pb_serdes_lane_swap_polarity_rx_phy11.BCM88650=0 |
| 324 | pb_serdes_lane_swap_polarity_rx_phy12.BCM88650=0 |
| 325 | pb_serdes_lane_swap_polarity_rx_phy13.BCM88650=0 |
| 326 | pb_serdes_lane_swap_polarity_rx_phy14.BCM88650=0 |
| 327 | pb_serdes_lane_swap_polarity_rx_phy15.BCM88650=0 |
| 328 | pb_serdes_lane_swap_polarity_rx_phy16.BCM88650=0 |
| 329 | pb_serdes_lane_swap_polarity_rx_phy17.BCM88650=0 |
| 330 | pb_serdes_lane_swap_polarity_rx_phy18.BCM88650=0 |
| 331 | pb_serdes_lane_swap_polarity_rx_phy19.BCM88650=0 |
| 332 | pb_serdes_lane_swap_polarity_rx_phy20.BCM88650=0 |
| 333 | pb_serdes_lane_swap_polarity_rx_phy21.BCM88650=0 |
| 334 | pb_serdes_lane_swap_polarity_rx_phy22.BCM88650=0 |
| 335 | pb_serdes_lane_swap_polarity_rx_phy23.BCM88650=0 |
| 336 | pb_serdes_lane_swap_polarity_rx_phy24.BCM88650=0 |
| 337 | pb_serdes_lane_swap_polarity_rx_phy25.BCM88650=0 |
| 338 | pb_serdes_lane_swap_polarity_rx_phy26.BCM88650=0 |
| 339 | pb_serdes_lane_swap_polarity_rx_phy27.BCM88650=0 |
| 340 | pb_serdes_lane_swap_polarity_rx_phy28.BCM88650=0 |
| 341 | |
| 342 | xgxs_tx_lane_map_quad0.BCM88650=0x3210 |
| 343 | xgxs_tx_lane_map_quad1.BCM88650=0x3210 |
| 344 | xgxs_tx_lane_map_quad2.BCM88650=0x3210 |
| 345 | xgxs_tx_lane_map_quad3.BCM88650=0x3210 |
| 346 | xgxs_tx_lane_map_quad4.BCM88650=0x3210 |
| 347 | xgxs_tx_lane_map_quad5.BCM88650=0x3210 |
| 348 | xgxs_tx_lane_map_quad6.BCM88650=0x3210 |
| 349 | |
| 350 | xgxs_rx_lane_map_quad0.BCM88650=0x3210 |
| 351 | xgxs_rx_lane_map_quad1.BCM88650=0x3210 |
| 352 | xgxs_rx_lane_map_quad2.BCM88650=0x3210 |
| 353 | xgxs_rx_lane_map_quad3.BCM88650=0x3210 |
| 354 | xgxs_rx_lane_map_quad4.BCM88650=0x3210 |
| 355 | xgxs_rx_lane_map_quad5.BCM88650=0x3210 |
| 356 | xgxs_rx_lane_map_quad6.BCM88650=0x3210 |
| 357 | |
| 358 | |
| 359 | |
| 360 | #High voltage driver strap. If 0, connected to 1.4V supply; if 1, connected to 1V mode. |
| 361 | #for specific quad use srd_tx_drv_hv_disable_quad_X where X is (FSRD num * 4 + internal quad) |
| 362 | srd_tx_drv_hv_disable.BCM88650=1 |
| 363 | |
| 364 | #Port init mode |
| 365 | #port_init_duplex=0 |
| 366 | #port_init_adv=0 |
| 367 | #port_init_autoneg=0 |
| 368 | |
| 369 | |
| 370 | # This disables serdes initialization |
| 371 | # phy_null.BCM88650=1 |
| 372 | |
| 373 | ## Number of Internal ports |
| 374 | # Enable the ERP port. Values: 0 / 1. |
| 375 | num_erp_tm_ports.BCM88650=1 |
| 376 | # Enable the OLP port. Values: 0 / 1. |
| 377 | num_olp_tm_ports.BCM88650=1 |
| 378 | # Enable OAMP |
| 379 | num_oamp_ports.BCM88650=0 |
| 380 | |
| 381 | ## Firmware Load Method |
| 382 | load_firmware.BCM88650=0x102 |
| 383 | |
| 384 | ### Headers configuration ### |
| 385 | |
| 386 | ## Use of the tm_port_header_type_<Local-Port-Id>=<Header-type> |
| 387 | ## Default header type is derived from fap_device_mode: If fap_device_mode is |
| 388 | ## PP, default header type is ETH. Otherwise, defualt header type is TM. |
| 389 | ## Header type per port can be overriden. |
| 390 | ## All options: ETH/RAW/TM/PROG/CPU/STACKING/TDM/TDM_RAW/UDH_ETH |
| 391 | ## Injected header types: if PTCH, INJECTED (local Port of type TM) or INJECTED_PP (PP) |
| 392 | ## if PTCH-2, INJECTED_2 (local Port of type TM) or INJECTED_2_PP (PP) |
| 393 | |
| 394 | # Set CPU to work with TM header (ITMH) |
| 395 | #tm_port_header_type_0.BCM88650=TM |
| 396 | |
| 397 | tm_port_header_type_in_180.BCM88650=INJECTED_2 |
| 398 | tm_port_header_type_out_180.BCM88650=CPU |
| 399 | |
| 400 | tm_port_header_type_in_200.BCM88650=INJECTED_2_PP |
| 401 | tm_port_header_type_out_200.BCM88650=ETH |
| 402 | tm_port_header_type_in_201.BCM88650=INJECTED_2_PP |
| 403 | tm_port_header_type_out_201.BCM88650=ETH |
| 404 | tm_port_header_type_in_202.BCM88650=INJECTED_2_PP |
| 405 | tm_port_header_type_out_202.BCM88650=ETH |
| 406 | tm_port_header_type_in_203.BCM88650=INJECTED_2_PP |
| 407 | tm_port_header_type_out_203.BCM88650=ETH |
| 408 | |
| 409 | ### Parser Configuration ### |
| 410 | # Parser has 4 custom macros that are allocated dynamically and |
| 411 | # configured according to the following features and soc properties: |
| 412 | # Trill (1 macro) - trill_mode |
| 413 | # FCoE (2 macros) - bcm886xx_fcoe_switch_mode |
| 414 | # VxLAN (1 macro) - bcm886xx_vxlan_enable |
| 415 | # IPv6-Extension-header (2 macros) - bcm886xx_ipv6_ext_hdr_enable |
| 416 | # UDP (1 macro) - UDP parsing is enabled by default, and can be |
| 417 | # disabled with soc property custom_feature_udp_parse_disable |
| 418 | # When disabling UDP parsing VxLAN and 1588oUDP are affected |
| 419 | |
| 420 | # Enable IPv6 Extension Header, 0 - disable (default), 1 - enable |
| 421 | #bcm886xx_ipv6_ext_hdr_enable=1 |
| 422 | |
| 423 | # Disable UDP parsing, 0 - enable (default), 1 - disable |
| 424 | #custom_feature_udp_parse_disable=1 |
| 425 | |
| 426 | #OAMP port |
| 427 | #tm_port_header_type_out_232.BCM88650=CPU |
| 428 | |
| 429 | #MPLS-TP channel types for OAM/BFD - If MPLS-TP used, channel should be specified |
| 430 | #Available types: mplstp_bfd_control_channel_type |
| 431 | # mplstp_pw_ach_channel_type |
| 432 | # mplstp_dlm_channel_type |
| 433 | # mplstp_ilm_channel_type |
| 434 | # mplstp_dm_channel_type |
| 435 | # mplstp_ipv4_channel_type |
| 436 | # mplstp_cc_channel_type |
| 437 | # mplstp_cv_channel_type |
| 438 | # mplstp_on_demand_cv_channel_type |
| 439 | # mplstp_pwe_oam_channel_type |
| 440 | # mplstp_ipv6_channel_type |
| 441 | # mplstp_fault_oam_channel_type |
| 442 | # mplstp_g8113_channel_type |
| 443 | #mplstp_g8113_channel_type=0x8902 |
| 444 | |
| 445 | |
| 446 | |
| 447 | # Set the recycling port processing to be raw (static forwarding) |
| 448 | tm_port_header_type_rcy.BCM88650=RAW |
| 449 | |
| 450 | ### RCPU |
| 451 | # Valid CPU local ports on which RCPU packets can be received by slave device. |
| 452 | #rcpu_rx_pbmp=0xf00000000000000000000000000000000000000000000000001 |
| 453 | |
| 454 | #tm_port_header_type_514.BCM88650=RAW |
| 455 | |
| 456 | ## Header extensions |
| 457 | # Set if an FTMH Out-LIF extension is present to Unicast and Multicast packets |
| 458 | # Options: NEVER / IF_MC (only Multicast packets) / ALWAYS |
| 459 | fabric_ftmh_outlif_extension.BCM88650=IF_MC |
| 460 | |
| 461 | # Set the FTMH Load-Balancing Key extension mode |
| 462 | # Options for 88660: ENABLED, FULL_HASH |
| 463 | # Options for 88650: ENABLED |
| 464 | # Options for 88640 compatible: DISABLED / 8B_LB_KEY_8B_STACKING_ROUTE_HISTORY / 16B_STACKING_ROUTE_HISTORY / |
| 465 | # STANDBY_MC_LB (available only for AradPlus) |
| 466 | # Default: DISABLED |
| 467 | system_ftmh_load_balancing_ext_mode.BCM88650=DISABLED |
| 468 | |
| 469 | # Set if an OTMH Out-LIF (CUD) Extension is present to Unicast and Multicast packets |
| 470 | # Options: NEVER / IF_MC (only Multicast packets) / ALWAYS / DOUBLE_TAG (two hop scheduling) |
| 471 | # Default: NEVER |
| 472 | # tm_port_otmh_outlif_ext_mode_13.BCM88650=NEVER |
| 473 | |
| 474 | # Set if an OTMH Source-System-Port Extension is present. |
| 475 | # Option: 0/1 |
| 476 | # Default: 0 |
| 477 | # tm_port_otmh_src_ext_enable_13.BCM88650=0 |
| 478 | |
| 479 | #Trunk hash format, relevant only for AradPlus. Possible values: NORMAL (default) / INVERTED / DUPLICATED. |
| 480 | #trunk_hash_format=NORMAL |
| 481 | |
| 482 | ## Stacking Application |
| 483 | #stacking_enable.BCM88650=1 |
| 484 | #custom_feature_stamp_uc_destination.BCM88650=1 |
| 485 | |
| 486 | ## System RED |
| 487 | # Set System-Red functionality. |
| 488 | #system_red_enable.BCM88650=1 |
| 489 | |
| 490 | # Indicate the size (Bytes) of a first header to skip |
| 491 | # before the major header at ingress (e.g. Ethernet, ITMH) |
| 492 | # It can be set per port also |
| 493 | first_header_size.BCM88650=0 |
| 494 | |
| 495 | # Indicate the size (Bytes) of the PMF Extension Headers |
| 496 | # to remove for TM header type ports (expecting ITMH) |
| 497 | # Set per port |
| 498 | #post_headers_size_0.BCM88650=4 |
| 499 | |
| 500 | # Indicate the size (Bytes) of the User-Headers: configurable |
| 501 | # headers located in the fabric between internal headers and |
| 502 | # Ethernet. Their values are set by Ingress FP, and can be used |
| 503 | # by Egress FP or Egress Editor. |
| 504 | # units: bits. 4 values can be set: |
| 505 | # 0 - size of the 1st User-Header, for the Egress PMF. 0b / 8b / 16b |
| 506 | # 1 - size of the 2nd User-Header, for the Egress PMF. 0b / 8b / 16b |
| 507 | # The sum of these 2 values should be under 16b |
| 508 | # 2, 3 - size of the 1st/2nd User-Header, for the Egress Editor. |
| 509 | # 0b / 8b / 16b / 24b / 32b |
| 510 | # Each of the global User-Header size must be under 32 bits, but not 24 bits. |
| 511 | # The Egress FP field is always at the MSB of the User-Header |
| 512 | # Not available for 88650-A0. |
| 513 | #field_class_id_size_0.BCM88650=8 |
| 514 | #field_class_id_size_1.BCM88650=0 |
| 515 | #field_class_id_size_2.BCM88650=24 |
| 516 | #field_class_id_size_3.BCM88650=0 |
| 517 | |
| 518 | |
| 519 | ### Trunk - LAG configuration ### |
| 520 | # Set Set the number of LAGs: 1024, 512, 256, 128 or 64 |
| 521 | number_of_trunks.BCM88650=256 |
| 522 | |
| 523 | ### SYNCE configuration ### |
| 524 | ## Synchronous Ethernet Signal Mode. |
| 525 | ## Options: TWO_DIFF_CLK, TWO_CLK_AND_VALID. Default: TWO_CLK_AND_VALID |
| 526 | #sync_eth_mode.BCM88650=TWO_CLK_AND_VALID |
| 527 | |
| 528 | ## Clock Source (single SerDes) lane in the specified NIF port. |
| 529 | ## Usage: sync_eth_clk_to_nif_id_clk_<clk_number>=<serdes_number> |
| 530 | #sync_eth_clk_to_nif_id_clk_0.BCM88650=1 |
| 531 | #sync_eth_clk_to_nif_id_clk_1.BCM88650=1 |
| 532 | |
| 533 | ## Clock Divider for the selected recovered clock. Valid values: 1/2/4. Default: 1. |
| 534 | ## Usage: sync_eth_clk_divider_clk_<clk_number>=<1/2/4> |
| 535 | #sync_eth_clk_divider_clk_0.BCM88650=1 |
| 536 | #sync_eth_clk_divider_clk_1.BCM88650=1 |
| 537 | |
| 538 | ## Enable the automatic squelch function for the recovered clock. Valid values: 0/1. Default: 0. |
| 539 | ## Usage: sync_eth_clk_squelch_enable_clk_<clk_number>=<0/1> |
| 540 | #sync_eth_clk_squelch_enable_clk_0.BCM88650=0 |
| 541 | #sync_eth_clk_squelch_enable_clk_1.BCM88650=0 |
| 542 | |
| 543 | ### ELK configuration ### |
| 544 | ## External lookup (TCAM) Device type select, Indicate the External lookup Device type. |
| 545 | # Value Options: NONE/NL88650. Default: NONE. |
| 546 | #ext_tcam_dev_type=NL88650 |
| 547 | |
| 548 | ## Set ELK FWD table Size. |
| 549 | # format: ext_xxx_fwd_table_size. |
| 550 | # where xxx replaced by FWD options: ip4_uc_rpf/ip4_mc/ip6_uc_rpf/ip6/ip6_mc/trill_uc/trill_mc/mpls/coup_mpls |
| 551 | # Value Options: (0) - External table disabled, >0: number of entries. Default: 0. |
| 552 | #ext_ip4_uc_rpf_fwd_table_size=8192 |
| 553 | #ext_ip4_mc_fwd_table_size=8192 |
| 554 | |
| 555 | ## Set ELK IP FWD use NetRoute ALG. |
| 556 | # Value Options: ALG_LPM_LPM/ALG_LPM_NETROUTE/ALG_LPM_TCAM. Default: ALG_LPM_TCAM. |
| 557 | #ext_fwd_algorithm_lpm=ALG_LPM_TCAM |
| 558 | |
| 559 | ## Set ELK interface mode. |
| 560 | # Change ELK interface configuration to support CAUI port. |
| 561 | # Value Options: 0/1. 0 - Normal mode, 1 2 CAUI port + ELK mode. Default: 0. |
| 562 | #ext_interface_mode=0 |
| 563 | |
| 564 | ### Configure MDIO interface |
| 565 | # External MDIO clock rate divisor . Default: 0x24. |
| 566 | #rate_ext_mdio_divisor=0x36 |
| 567 | # External MDIO clock rate divisor. Default: 0x1. |
| 568 | #rate_ext_mdio_dividend=1 |
| 569 | |
| 570 | ### TDM - OTN configuration ### |
| 571 | #fap_tdm_bypass.BCM88650=0 |
| 572 | |
| 573 | # Indicate if a Petra-B device is connected to the actual device |
| 574 | # For TDM/OTN applications, |
| 575 | # system_is_petra_b_in_system.BCM88650=0 |
| 576 | ##Indicate if TDM can arrive throgh primary pipe. |
| 577 | #Should be 1 for a System with PetraB that connected to fabric over primary pipe. |
| 578 | fabric_tdm_over_primary_pipe.BCM88650=0 |
| 579 | |
| 580 | ### Fabric configuration ### |
| 581 | #0-LFEC 1-8b\10b 2-FEC 3-BEC |
| 582 | backplane_serdes_encoding.BCM88650=2 |
| 583 | #SFI speed rate |
| 584 | port_init_speed_sfi.BCM88650=10312 |
| 585 | #CL72 |
| 586 | #port_init_cl72_sfi=0 |
| 587 | fabric_segmentation_enable.BCM88650=1 |
| 588 | |
| 589 | ## Fabric transmission mode |
| 590 | # Set the Connect mode to the Fabric |
| 591 | # Options: FE - presence of a Fabric device (single stage) / MULT_STAGE_FE - Multi-stage / |
| 592 | # SINGLE_FAP - stand-alone device / MESH - mesh / BACK2BACK - 2 devices in Mesh |
| 593 | fabric_connect_mode.BCM88650=SINGLE_FAP |
| 594 | #fabric_connect_mode.BCM88650=FE |
| 595 | |
| 596 | ## Cell format configuration |
| 597 | # Indicate if the traffic can be sent in dual pipe |
| 598 | is_dual_mode.BCM88650=0 |
| 599 | # Indicate the format of the cell: |
| 600 | # A VCS128 cell is used if system_is_vcs_128_in_system or system_is_fe600_in_system is TRUE |
| 601 | system_is_vcs_128_in_system.BCM88650=0 |
| 602 | system_is_fe600_in_system.BCM88650=0 |
| 603 | |
| 604 | ### WRED ### |
| 605 | |
| 606 | # Set the maximum packet size for WRED tests. 0 - means ignore max packet size. |
| 607 | discard_mtu_size.BCM88650=0 |
| 608 | |
| 609 | ### OCB (On-Chip Buffer) configuration ### |
| 610 | # Enable the OCB |
| 611 | # Enable MODES: |
| 612 | # 0/FALSE --> OCB_DISABLED --> No OCB use |
| 613 | # 1/TRUE --> OCB_ENABLED --> Like in Arad-A0/B0. Some packets may use both DRAM and OCB resources |
| 614 | # ONE_WAY_BYPASS --> Depends on number of present drams (available only for AradPlus): |
| 615 | # 0 drams: - OCB_ONLY |
| 616 | # 1 drams: - OCB_ONLY_1_DRAM --> : OCB-only with 1 DRAM for the free pointers |
| 617 | # 2-8 drams: - OCB_DRAM_SEPARATE --> : OCB and DRAM coexist separately |
| 618 | # Default: TRUE. |
| 619 | bcm886xx_ocb_enable.BCM88650=1 |
| 620 | |
| 621 | # OCB Data Buffer size. Possible values: 128/256/512/1024. Default: 256. |
| 622 | bcm886xx_ocb_databuffer_size.BCM88650=256 |
| 623 | # Repartition between Unicast and Full Multicast buffers. |
| 624 | # 0: 80% Unicast and 20% Multicast, 1: Unicast-Only |
| 625 | bcm886xx_ocb_repartition.BCM88650=0 |
| 626 | |
| 627 | ### PDM configuration ### |
| 628 | # Set the PDM Mode. |
| 629 | # 0: simple (default), 1: reduced (mandatory for LLFC-VSQ, PFC-VSQ, or ST-VSQ) |
| 630 | bcm886xx_pdm_mode.BCM88650=0 |
| 631 | |
| 632 | ### Multicast Number of DBuff mode ### |
| 633 | # Set IQM FMC buffers-replication sizes |
| 634 | # Options for 88650: ARAD_INIT_FMC_4K_REP_64K_DBUFF_MODE/ARAD_INIT_FMC_64_REP_128K_DBUFF_MODE |
| 635 | # Default: ARAD_INIT_FMC_4K_REP_64K_DBUFF_MODE |
| 636 | multicast_nbr_full_dbuff.BCM88650=ARAD_INIT_FMC_4K_REP_64K_DBUFF_MODE |
| 637 | |
| 638 | ### Multicast configuration ### |
| 639 | # Multicast egress vlan membership range. By default: 0-4095. |
| 640 | egress_multicast_direct_bitmap_min.BCM88650=0 |
| 641 | egress_multicast_direct_bitmap_max.BCM88650=4095 |
| 642 | |
| 643 | ### VOQ - Flow configuration ### |
| 644 | |
| 645 | # Set the VOQ mapping mode: |
| 646 | # DIRECT: More than 4K System Ports are supported. System-level WRED is not supported. |
| 647 | # INDIRECT: similar to Petra-B. Up to 4K System Ports. |
| 648 | voq_mapping_mode.BCM88650=INDIRECT |
| 649 | |
| 650 | # Set the Base Queue to be added to the packet flow-id |
| 651 | # when the Flow-Id is set explicitely either by the ITMH |
| 652 | # or by the Destination resolution in the Packet processing |
| 653 | flow_mapping_queue_base.BCM88650=0 |
| 654 | |
| 655 | # Set the number of priorities supported at egress per Port |
| 656 | # Options: 1 / 2 / 8 |
| 657 | port_priorities.BCM88650=8 |
| 658 | |
| 659 | # Set the shared multicast resource mode: Strict / Discrete |
| 660 | egress_shared_resources_mode.BCM88650=Strict |
| 661 | |
| 662 | # Define outgoing port rate mode in data rate or packet rate. |
| 663 | # Options: DATA / PACKET |
| 664 | otm_port_packet_rate.BCM88650=DATA |
| 665 | |
| 666 | # Set Port egress recycling scheduler configuration. |
| 667 | # 0: Strict Priority Scheduler, 1: Round Robin Scheduler |
| 668 | port_egress_recycling_scheduler_configuration.BCM88650=0 |
| 669 | |
| 670 | # Set statically the region mode per region id |
| 671 | # 0: queue connectors only (InterDigitated = FALSE, OddEven = TRUE) |
| 672 | # 1: queue connectors, SE (InterDigitated =TRUE, OddEven = TRUE) |
| 673 | # 2: queue connectors, SE (InterDigitated =TRUE, OddEven = FALSE) |
| 674 | dtm_flow_mapping_mode_region_65.BCM88650=0 |
| 675 | dtm_flow_mapping_mode_region_66.BCM88650=0 |
| 676 | dtm_flow_mapping_mode_region_67.BCM88650=0 |
| 677 | dtm_flow_mapping_mode_region_68.BCM88650=0 |
| 678 | dtm_flow_mapping_mode_region_69.BCM88650=0 |
| 679 | dtm_flow_mapping_mode_region_70.BCM88650=0 |
| 680 | dtm_flow_mapping_mode_region_71.BCM88650=0 |
| 681 | dtm_flow_mapping_mode_region_72.BCM88650=0 |
| 682 | dtm_flow_mapping_mode_region_73.BCM88650=0 |
| 683 | dtm_flow_mapping_mode_region_74.BCM88650=0 |
| 684 | dtm_flow_mapping_mode_region_75.BCM88650=0 |
| 685 | dtm_flow_mapping_mode_region_76.BCM88650=0 |
| 686 | dtm_flow_mapping_mode_region_77.BCM88650=0 |
| 687 | dtm_flow_mapping_mode_region_78.BCM88650=0 |
| 688 | dtm_flow_mapping_mode_region_79.BCM88650=0 |
| 689 | dtm_flow_mapping_mode_region_80.BCM88650=0 |
| 690 | dtm_flow_mapping_mode_region_81.BCM88650=1 |
| 691 | dtm_flow_mapping_mode_region_82.BCM88650=1 |
| 692 | dtm_flow_mapping_mode_region_83.BCM88650=1 |
| 693 | dtm_flow_mapping_mode_region_84.BCM88650=1 |
| 694 | dtm_flow_mapping_mode_region_85.BCM88650=1 |
| 695 | dtm_flow_mapping_mode_region_86.BCM88650=1 |
| 696 | dtm_flow_mapping_mode_region_87.BCM88650=1 |
| 697 | dtm_flow_mapping_mode_region_88.BCM88650=1 |
| 698 | dtm_flow_mapping_mode_region_89.BCM88650=1 |
| 699 | dtm_flow_mapping_mode_region_90.BCM88650=1 |
| 700 | dtm_flow_mapping_mode_region_91.BCM88650=1 |
| 701 | dtm_flow_mapping_mode_region_92.BCM88650=1 |
| 702 | dtm_flow_mapping_mode_region_93.BCM88650=1 |
| 703 | dtm_flow_mapping_mode_region_94.BCM88650=1 |
| 704 | dtm_flow_mapping_mode_region_95.BCM88650=1 |
| 705 | dtm_flow_mapping_mode_region_96.BCM88650=1 |
| 706 | dtm_flow_mapping_mode_region_97.BCM88650=1 |
| 707 | dtm_flow_mapping_mode_region_98.BCM88650=1 |
| 708 | dtm_flow_mapping_mode_region_99.BCM88650=2 |
| 709 | dtm_flow_mapping_mode_region_100.BCM88650=2 |
| 710 | dtm_flow_mapping_mode_region_101.BCM88650=2 |
| 711 | dtm_flow_mapping_mode_region_102.BCM88650=2 |
| 712 | dtm_flow_mapping_mode_region_103.BCM88650=2 |
| 713 | dtm_flow_mapping_mode_region_104.BCM88650=2 |
| 714 | dtm_flow_mapping_mode_region_105.BCM88650=2 |
| 715 | dtm_flow_mapping_mode_region_106.BCM88650=2 |
| 716 | dtm_flow_mapping_mode_region_107.BCM88650=2 |
| 717 | dtm_flow_mapping_mode_region_108.BCM88650=2 |
| 718 | dtm_flow_mapping_mode_region_109.BCM88650=2 |
| 719 | dtm_flow_mapping_mode_region_110.BCM88650=2 |
| 720 | dtm_flow_mapping_mode_region_111.BCM88650=2 |
| 721 | dtm_flow_mapping_mode_region_112.BCM88650=2 |
| 722 | dtm_flow_mapping_mode_region_113.BCM88650=2 |
| 723 | dtm_flow_mapping_mode_region_114.BCM88650=2 |
| 724 | dtm_flow_mapping_mode_region_115.BCM88650=2 |
| 725 | dtm_flow_mapping_mode_region_116.BCM88650=2 |
| 726 | dtm_flow_mapping_mode_region_117.BCM88650=2 |
| 727 | dtm_flow_mapping_mode_region_118.BCM88650=2 |
| 728 | dtm_flow_mapping_mode_region_119.BCM88650=2 |
| 729 | dtm_flow_mapping_mode_region_120.BCM88650=2 |
| 730 | dtm_flow_mapping_mode_region_121.BCM88650=2 |
| 731 | dtm_flow_mapping_mode_region_122.BCM88650=2 |
| 732 | dtm_flow_mapping_mode_region_123.BCM88650=2 |
| 733 | dtm_flow_mapping_mode_region_124.BCM88650=2 |
| 734 | dtm_flow_mapping_mode_region_125.BCM88650=2 |
| 735 | dtm_flow_mapping_mode_region_126.BCM88650=2 |
| 736 | dtm_flow_mapping_mode_region_127.BCM88650=2 |
| 737 | dtm_flow_mapping_mode_region_128.BCM88650=2 |
| 738 | |
| 739 | #IL# Configure number of symmetric cores each region supports ## |
| 740 | dtm_flow_nof_remote_cores_region_1.BCM88650=2 |
| 741 | dtm_flow_nof_remote_cores_region_2.BCM88650=2 |
| 742 | dtm_flow_nof_remote_cores_region_3.BCM88650=2 |
| 743 | dtm_flow_nof_remote_cores_region_4.BCM88650=2 |
| 744 | dtm_flow_nof_remote_cores_region_5.BCM88650=2 |
| 745 | dtm_flow_nof_remote_cores_region_6.BCM88650=2 |
| 746 | dtm_flow_nof_remote_cores_region_7.BCM88650=2 |
| 747 | dtm_flow_nof_remote_cores_region_8.BCM88650=2 |
| 748 | dtm_flow_nof_remote_cores_region_9.BCM88650=2 |
| 749 | dtm_flow_nof_remote_cores_region_10.BCM88650=2 |
| 750 | dtm_flow_nof_remote_cores_region_11.BCM88650=2 |
| 751 | dtm_flow_nof_remote_cores_region_12.BCM88650=2 |
| 752 | dtm_flow_nof_remote_cores_region_13.BCM88650=2 |
| 753 | dtm_flow_nof_remote_cores_region_14.BCM88650=2 |
| 754 | dtm_flow_nof_remote_cores_region_15.BCM88650=2 |
| 755 | dtm_flow_nof_remote_cores_region_16.BCM88650=2 |
| 756 | dtm_flow_nof_remote_cores_region_17.BCM88650=2 |
| 757 | dtm_flow_nof_remote_cores_region_18.BCM88650=2 |
| 758 | dtm_flow_nof_remote_cores_region_19.BCM88650=2 |
| 759 | dtm_flow_nof_remote_cores_region_20.BCM88650=2 |
| 760 | dtm_flow_nof_remote_cores_region_21.BCM88650=2 |
| 761 | dtm_flow_nof_remote_cores_region_22.BCM88650=2 |
| 762 | dtm_flow_nof_remote_cores_region_23.BCM88650=2 |
| 763 | dtm_flow_nof_remote_cores_region_24.BCM88650=2 |
| 764 | dtm_flow_nof_remote_cores_region_25.BCM88650=2 |
| 765 | dtm_flow_nof_remote_cores_region_26.BCM88650=2 |
| 766 | dtm_flow_nof_remote_cores_region_27.BCM88650=2 |
| 767 | dtm_flow_nof_remote_cores_region_28.BCM88650=2 |
| 768 | dtm_flow_nof_remote_cores_region_29.BCM88650=2 |
| 769 | dtm_flow_nof_remote_cores_region_30.BCM88650=2 |
| 770 | dtm_flow_nof_remote_cores_region_31.BCM88650=2 |
| 771 | dtm_flow_nof_remote_cores_region_32.BCM88650=2 |
| 772 | dtm_flow_nof_remote_cores_region_33.BCM88650=2 |
| 773 | dtm_flow_nof_remote_cores_region_34.BCM88650=2 |
| 774 | dtm_flow_nof_remote_cores_region_35.BCM88650=2 |
| 775 | dtm_flow_nof_remote_cores_region_36.BCM88650=2 |
| 776 | dtm_flow_nof_remote_cores_region_37.BCM88650=2 |
| 777 | dtm_flow_nof_remote_cores_region_38.BCM88650=2 |
| 778 | dtm_flow_nof_remote_cores_region_39.BCM88650=2 |
| 779 | dtm_flow_nof_remote_cores_region_40.BCM88650=2 |
| 780 | dtm_flow_nof_remote_cores_region_41.BCM88650=2 |
| 781 | dtm_flow_nof_remote_cores_region_42.BCM88650=2 |
| 782 | dtm_flow_nof_remote_cores_region_43.BCM88650=2 |
| 783 | dtm_flow_nof_remote_cores_region_44.BCM88650=2 |
| 784 | dtm_flow_nof_remote_cores_region_45.BCM88650=2 |
| 785 | dtm_flow_nof_remote_cores_region_46.BCM88650=2 |
| 786 | dtm_flow_nof_remote_cores_region_47.BCM88650=2 |
| 787 | dtm_flow_nof_remote_cores_region_48.BCM88650=2 |
| 788 | dtm_flow_nof_remote_cores_region_49.BCM88650=2 |
| 789 | dtm_flow_nof_remote_cores_region_50.BCM88650=2 |
| 790 | dtm_flow_nof_remote_cores_region_51.BCM88650=2 |
| 791 | dtm_flow_nof_remote_cores_region_52.BCM88650=2 |
| 792 | dtm_flow_nof_remote_cores_region_53.BCM88650=2 |
| 793 | dtm_flow_nof_remote_cores_region_54.BCM88650=2 |
| 794 | dtm_flow_nof_remote_cores_region_55.BCM88650=2 |
| 795 | dtm_flow_nof_remote_cores_region_56.BCM88650=2 |
| 796 | dtm_flow_nof_remote_cores_region_57.BCM88650=2 |
| 797 | dtm_flow_nof_remote_cores_region_58.BCM88650=2 |
| 798 | dtm_flow_nof_remote_cores_region_59.BCM88650=2 |
| 799 | dtm_flow_nof_remote_cores_region_60.BCM88650=2 |
| 800 | |
| 801 | dtm_flow_nof_remote_cores_region_core0_2.BCM88650=1 |
| 802 | dtm_flow_nof_remote_cores_region_core0_3.BCM88650=1 |
| 803 | |
| 804 | ### Flow Control configuration ### |
| 805 | # Set the Flow control type per Port. |
| 806 | # Options: LL (Link-level) / CB2 (Class-Based - 2 classes) / |
| 807 | # CB8 (Class-Based - 8 classes) |
| 808 | # flow_control_type.BCM88650=LL |
| 809 | |
| 810 | ## Out-Of-Band Flow control configuration |
| 811 | #spn_FC_OOB_TYPE, spn_FC_OOB_MODE, spn_FC_OOB_CALENDER_LENGTH, spn_FC_OOB_CALENDER_REP_COUNT, |
| 812 | |
| 813 | ## Set voltage mode for oob interfaces |
| 814 | #HSTL_1.5V |
| 815 | #3.3V |
| 816 | #HSTL_1.5V_VDDO_DIV_2 |
| 817 | ext_voltage_mode_oob=3.3V |
| 818 | |
| 819 | ## Inband Interlaken configuration |
| 820 | # spn_FC_INBAND_INTLKN_MODE, spn_FC_INBAND_INTLKN_CALENDER_LENGTH, spn_FC_INBAND_INTLKN_CALENDER_REP_COUNT |
| 821 | # spn_FC_INBAND_INTLKN_CALENDER_LLFC_MODE, spn_FC_INBAND_INTLKN_LLFC_MUB_ENABLE_MASK |
| 822 | |
| 823 | ### Meter engine configuration ### |
| 824 | |
| 825 | # Specify meter operation mode |
| 826 | # 32 - Two meters per packet (32k total) |
| 827 | # 64 - One meter per packet (64k total) |
| 828 | # Options: 0, 32, 64 |
| 829 | policer_ingress_count.BCM88650=32 |
| 830 | |
| 831 | # For meters in double 32k mode, determine the sharing mode |
| 832 | # Options: |
| 833 | # 0 - NONE (only for 64k mode) |
| 834 | # 1 - SERIAL (only for 32k mode) |
| 835 | # 2 - PARALLEL (only for 32k mode) |
| 836 | policer_ingress_sharing_mode.BCM88650=1 |
| 837 | |
| 838 | # Applies only to Arad+ (88660) |
| 839 | # For meters in parallel mode, determine the mapping |
| 840 | # Options: BEST, WORST |
| 841 | # policer_result_parallel_color_map.BCM88650=WORST |
| 842 | |
| 843 | # Applies only to Arad+ (88660) |
| 844 | # For meters in parallel mode, determine how the buckets are changed |
| 845 | # Options: CONSTANT, TRANSPARENT, DEFERRED |
| 846 | # policer_result_parallel_bucket_update.BCM88650=CONSTANT |
| 847 | |
| 848 | # Applies only to Arad+ (88660) |
| 849 | # Set the Ethernet policer to work in color blind mode |
| 850 | # rate_color_blind.BCM88650=1 |
| 851 | |
| 852 | # L2 learn limit mode |
| 853 | # Options: VLAN, VLAN_PORT, TUNNEL or the numeric equivalent 0-2. |
| 854 | # Default: VLAN |
| 855 | # l2_learn_limit_mode = VLAN_PORT |
| 856 | |
| 857 | # Applies only to Arad+ (88660) |
| 858 | # Determines the L2 learn limit ranges when l2_learn_limit_mode is set to VLAN_PORT |
| 859 | # Two range bases can be selected, each of 16K size. |
| 860 | # Options: 0, 16K, 32K, 48K. |
| 861 | # Default: 0 & 16K |
| 862 | # l2_learn_lif_range_base_0 = 0 |
| 863 | # l2_learn_lif_range_base_1 = 16K |
| 864 | |
| 865 | ### Counter engine configuration ### |
| 866 | |
| 867 | # Set the Counter source |
| 868 | # Options: INGRESS_FIELD / INGRESS_VOQ / INGRESS_VSQ |
| 869 | # INGRESS_CNM / EGRESS_FIELD / EGRESS_VSI / EGRESS_OUT_LIF / EGRESS_TM (per queue) / EGRESS_TM_PORT (per port) |
| 870 | # EGRESS_RECEIVE_VSI / EGRESS_RECEIVE_OUT_LIF / EGRESS_RECEIVE_TM (per queue) / EGRESS_RECEIVE_TM_PORT (per port) |
| 871 | # INGRESS_OAM / EGRESS_OAM |
| 872 | # 2 Counter-Pointers can be set (with _0 and _1) for |
| 873 | # INGRESS_FIELD / EGRESS_VSI / EGRESS_OUT_LIF / EGRESS_TM / EGRESS_TM_PORT |
| 874 | # Range extension can be set (with _LSB and _MSB) for |
| 875 | # INGRESS_FIELD / EGRESS_VSI / EGRESS_OUT_LIF / EGRESS_TM / EGRESS_TM_PORT /EGRESS_RECEIVE_VSI / |
| 876 | # EGRESS_RECEIVE_OUT_LIF / EGRESS_RECEIVE_TM / EGRESS_RECEIVE_TM_PORT |
| 877 | counter_engine_source_0.BCM88650=INGRESS_FIELD |
| 878 | counter_engine_source_1.BCM88650=INGRESS_FIELD_1 |
| 879 | counter_engine_source_2.BCM88650=INGRESS_VOQ |
| 880 | ### |
| 881 | ### DML |
| 882 | ### |
| 883 | ### For DML applications, counter engine 3 is used for VOQ |
| 884 | ### counters. This in combination with configuring the engines used for |
| 885 | ### VOQs for FWD_DROP allows for counters for 32K VOQs. |
| 886 | ### |
| 887 | #counter_engine_source_3.BCM88650=EGRESS_FIELD |
| 888 | counter_engine_source_3.BCM88650=INGRESS_VOQ |
| 889 | |
| 890 | # Configure the statistic interface egress source |
| 891 | # Options: EGRESS_VSI / EGRESS_OUT_LIF / EGRESS_TM / EGRESS_TM_PORT (the default is TM) |
| 892 | # valid just when there is no conflict with the other counter engines |
| 893 | #counter_engine_source_stat0.BCM88650=EGRESS_TM |
| 894 | #counter_engine_source_stat1.BCM88650=EGRESS_TM |
| 895 | |
| 896 | |
| 897 | # Set the Counter engine resolution |
| 898 | # SIMPLE_COLOR = green, not green |
| 899 | # SIMPLE_COLOR_FWD = fwd green, fwd not green (BCM88660_A0 only) |
| 900 | # SIMPLE_COLOR_DROP = drop green, drop not green (BCM88660_A0 only) |
| 901 | # FWD_DROP = forwarded, dropped |
| 902 | # GREEN_NOT_GREEN = fwd grn, drop grn, fwd not grn, drop not grn |
| 903 | # FULL_COLOR = fwd grn, drop grn, fwd not grn, drop yel, drop red |
| 904 | # ALL = received |
| 905 | # FWD = forwarded, DROP = droped (not supported by ARAD_A0) |
| 906 | # CONFIGURABLE = defined by counter_engine_map_ SOC properties (BCM88660_A0 only) |
| 907 | counter_engine_statistics_0.BCM88650=FULL_COLOR |
| 908 | counter_engine_statistics_1.BCM88650=FULL_COLOR |
| 909 | ### |
| 910 | ### DML |
| 911 | ### |
| 912 | ### For DML applications, counter engine 3 is used for VOQ |
| 913 | ### counters. This in combination with configuring the engines used for |
| 914 | ### VOQs for FWD_DROP allows for counters for 32K VOQs. |
| 915 | ### |
| 916 | #counter_engine_statistics_2.BCM88650=FULL_COLOR |
| 917 | #counter_engine_statistics_3.BCM88650=FULL_COLOR |
| 918 | counter_engine_statistics_2.BCM88650=FWD_DROP |
| 919 | counter_engine_statistics_3.BCM88650=FWD_DROP |
| 920 | |
| 921 | # Set the Counter format |
| 922 | # Options: PACKETS_AND_BYTES / PACKETS / BYTES |
| 923 | # / MAX_QUEUE_SIZE / PACKETS_AND_PACKETS(supported just in FWD_DROP statistic in BCM88660_A0) |
| 924 | # If not PACKETS_AND_BYTES or PACKETS_AND_PACKETS, the HW Counter width is 59 bits, thus |
| 925 | # no background SW operation is performed |
| 926 | counter_engine_format_0.BCM88650=PACKETS_AND_BYTES |
| 927 | counter_engine_format_1.BCM88650=PACKETS_AND_BYTES |
| 928 | counter_engine_format_2.BCM88650=PACKETS_AND_BYTES |
| 929 | counter_engine_format_3.BCM88650=PACKETS_AND_BYTES |
| 930 | |
| 931 | # #enable/disable counter processor background thread (default:1-enable) |
| 932 | # counter_engine_sampling_interval=1 |
| 933 | |
| 934 | ### Configurable mode configuration (BCM88660_A0 only)### |
| 935 | # counter_engine_statistics_0.BCM88660_A0=CONFIGURABLE |
| 936 | # counter_engine_map_enable_0.BCM88660_A0=1 |
| 937 | # counter_engine_map_size_0.BCM88660_A0=4 |
| 938 | # counter_engine_map_fwd_green_offset_0.BCM88660_A0=0 |
| 939 | # counter_engine_map_fwd_yellow_offset_0.BCM88660_A0=1 |
| 940 | # counter_engine_map_fwd_red_offset_0.BCM88660_A0=1 |
| 941 | # counter_engine_map_fwd_black_offset_0.BCM88660_A0=2 |
| 942 | # counter_engine_map_drop_green_offset_0.BCM88660_A0=3 |
| 943 | # counter_engine_map_drop_yellow_offset_0.BCM88660_A0=3 |
| 944 | # counter_engine_map_drop_red_offset_0.BCM88660_A0=3 |
| 945 | # counter_engine_map_drop_black_offset_0.BCM88660_A0=3 |
| 946 | |
| 947 | ### Statistic-Report configuration ### |
| 948 | # Enable the Statistic-Interface configuration |
| 949 | # stat_if_enable_<port> - not supported by ARAD_A0 |
| 950 | # stat_if_enable.BCM88650=1 |
| 951 | |
| 952 | # ## Statistic-Report Properties |
| 953 | # # Set the Statistic-Report mode |
| 954 | # # Options: BILLING / BILLING_QUEUE_NUMBER (not supported by ARAD_A0)/ QSIZE |
| 955 | # stat_if_report_mode.BCM88650=QSIZE |
| 956 | # #Indicate if idle reports must be sent |
| 957 | # #when the Statistic-report rate is too low |
| 958 | # stat_if_idle_reports_present.BCM88650=0 |
| 959 | # # Indicate if the reported packet size is the original packet size |
| 960 | # stat_if_report_original_pkt_size.BCM88650=1 |
| 961 | # #If set then a single ingress-billing report will be generated |
| 962 | # #for the whole set of the multicast copies |
| 963 | # stat_if_report_multicast_single_copy=1 |
| 964 | # ## Statistic Packet configurations |
| 965 | # # Set the Statistic Packet size (Bytes) |
| 966 | # # Valid valued: 65B/126B/248B/492B (Queue-Size), 64B/128B/256B/512B/1024B (Billing) |
| 967 | # stat_if_pkt_size=64B |
| 968 | # |
| 969 | # ## Scrubber configuration |
| 970 | # # Set the range of VOQs to scrub. Range: 0 - 96K-1. |
| 971 | # stat_if_scrubber_queue_min.BCM88650=0 |
| 972 | # stat_if_scrubber_queue_max.BCM88650=0 |
| 973 | # |
| 974 | # # Set the scrubber rate range |
| 975 | # # If set to 0 (default), the scrubber is disabled. Units: nanoseconds |
| 976 | # stat_if_scrubber_rate_min.BCM88650=0 |
| 977 | # stat_if_scrubber_rate_max.BCM88650=0 |
| 978 | # |
| 979 | # # Set the thresholds (thresh_id 0 - 15) defining |
| 980 | # # occupancy range per resource type: |
| 981 | # # DRAM Buffers, Buffer descriptors, Buffer descriptors buffers |
| 982 | # stat_if_scrubber_bdb_th.BCM88650=0 |
| 983 | # stat_if_scrubber_buffer_descr_th.BCM88650=0 |
| 984 | # stat_if_uc_dram_buffer_descr_th.BCM88650=0 |
| 985 | # |
| 986 | # #Relective report for queue size mode - not supported by ARAD_A0 |
| 987 | # #Reports will be created for queue num range (stat_if_selective_report_queue_min -stat_if_selective_report_queue_max) |
| 988 | # #Default - all range |
| 989 | # stat_if_selective_report_queue_min.BCM88650_B0=0 |
| 990 | # stat_if_selective_report_queue_max.BCM88650_B0=98303 |
| 991 | |
| 992 | ### Transaction - DMA configuration ### |
| 993 | # Time to wait for SCHAN channel response (from CMIC). Units: microseconds. |
| 994 | |
| 995 | # TODO |
| 996 | ### Counter threads ### |
| 997 | # spn_BCM_STAT_PBMP, spn_BCM_STAT_INTERVAL, spn_BCM_STAT_FLAGS |
| 998 | |
| 999 | ### Interrupts ### |
| 1000 | ## Set interrupts global parameters. |
| 1001 | # Options: 1 - Polling interrupt mode, 0 - Line/MSI interrupt mode. Default: 1. |
| 1002 | polled_irq_mode.BCM88650=0 |
| 1003 | # Set the delay in microsecond between the polling, relevant only to Polling mode. Default: 0x0. |
| 1004 | polled_irq_delay.BCM88650=50000 |
| 1005 | |
| 1006 | ## CMIC interrupts: |
| 1007 | # Enable: Use interrupts completion instead of polling completion for the following operations. |
| 1008 | # Options: 1 - Enable, 0 - Disable. Default: 0. |
| 1009 | # Timeout: delay in Microsecond between the polling, relevant only to Polling completion mode. |
| 1010 | # SCHAN: |
| 1011 | #schan_intr_enable.0=1 |
| 1012 | schan_timeout_usec.BCM88650=300000 |
| 1013 | # TDMA |
| 1014 | tdma_intr_enable.BCM88650=1 |
| 1015 | tdma_timeout_usec.BCM88650=80000000 |
| 1016 | # TSLAM |
| 1017 | tslam_intr_enable.BCM88650=1 |
| 1018 | tslam_timeout_usec.BCM88650=80000000 |
| 1019 | # MIIM |
| 1020 | #miim_intr_enable.0=1 |
| 1021 | miim_timeout_usec.0=300000 |
| 1022 | |
| 1023 | ### DRAM configuration ### |
| 1024 | |
| 1025 | # DRAM buffer (Dbuff) size |
| 1026 | # Allowed values: 256/512/1024/2048. |
| 1027 | ext_ram_dbuff_size.BCM88650=1024 |
| 1028 | |
| 1029 | # Number of external DRAMs. |
| 1030 | # Allowed values for 88650: 0/2/3/4/6/8. A value of 0 disables the DRAM. |
| 1031 | # Allowed values for 88660: 0/1/2/3/4/6/8. A value of 0 disables the DRAM. |
| 1032 | # A value of 1 is permitted only in ONE WAY BYPASS ocb mode. |
| 1033 | ext_ram_present.BCM88650=8 |
| 1034 | |
| 1035 | ### Dram Tuning (Shmoo) |
| 1036 | # 2 = Use Dram saved config Parameters, if no Parameters Perform Shmoo on init. Default option. |
| 1037 | # 1 = Perform Shmoo on init. |
| 1038 | # 0 = Use Dram saved config Parameters, if no Parameters do nothing. |
| 1039 | ddr3_auto_tune.BCM88650=2 |
| 1040 | |
| 1041 | ### Enable BIST |
| 1042 | # Run Dram BIST on initialization, if BIST fail the initialization will fail. Defult: 1. |
| 1043 | # bist_enable_dram.BCM88650=1 |
| 1044 | |
| 1045 | ### Example for Dram Saved config Parameters. |
| 1046 | ## This example is for ci=14 (Dram=7). |
| 1047 | #ddr3_tune_addrc_ci14=0x000000ae |
| 1048 | #ddr3_tune_wr_dq_wl1_ci14=0x92929292,0x92929292,0x92929292,0x92929292 |
| 1049 | #ddr3_tune_wr_dq_wl0_ci14=0x93939393,0x93939393,0x92929292,0x92929292 |
| 1050 | #ddr3_tune_wr_dq_ci14=0x80808080 |
| 1051 | #ddr3_tune_vref_ci14=0x000007df |
| 1052 | #ddr3_tune_rd_dqs_ci14=0x96969191,0x90909191 |
| 1053 | #ddr3_tune_rd_dq_wl1_rn_ci14=0x82828282,0x82828282,0x82828282,0x82828282 |
| 1054 | #ddr3_tune_rd_dq_wl0_rn_ci14=0x82828282,0x82828282,0x89898989,0x89898989 |
| 1055 | #ddr3_tune_rd_dq_wl1_rp_ci14=0x82828282,0x82828282,0x82828282,0x82828282 |
| 1056 | #ddr3_tune_rd_dq_wl0_rp_ci14=0x82828282,0x82828282,0x89898989,0x89898989 |
| 1057 | #ddr3_tune_rd_en_ci14=0x009d9e9d,0x00a2a3a1 |
| 1058 | #ddr3_tune_rd_data_dly_ci14=0x00000505 |
| 1059 | ddr3_tune_rd_dq_wl1_rp_ci8.0=0x82828282,0x82828282,0x8b8b8b8b,0x8b8b8b8b |
| 1060 | ddr3_tune_wr_dq_wl0_ci4.0=0x93939393,0x93939393,0x92929292,0x92929292 |
| 1061 | ddr3_tune_vref_ci10.0=0x0000079e |
| 1062 | ddr3_tune_wr_dq_wl1_ci2.0=0x92929292,0x92929292,0x92929292,0x92929292 |
| 1063 | ddr3_tune_wr_dq_ci6.0=0x80808080 |
| 1064 | ddr3_tune_rd_dq_wl0_rn_ci6.0=0x80808080,0x80808080,0x8c8c8c8c,0x8c8c8c8c |
| 1065 | ddr3_tune_rd_dq_wl1_rp_ci10.0=0x83838383,0x83838383,0x84848484,0x84848484 |
| 1066 | ddr3_tune_rd_dqs_ci8.0=0x96969797,0x94949090 |
| 1067 | ddr3_tune_vref_ci6.0=0x0000079e |
| 1068 | ddr3_tune_rd_dq_wl0_rp_ci14.0=0x83838383,0x83838383,0x83838383,0x83838383 |
| 1069 | ddr3_tune_rd_en_ci10.0=0x009fa09f,0x009a9c99 |
| 1070 | ddr3_tune_rd_data_dly_ci4.0=0x00000404 |
| 1071 | ddr3_tune_addrc_ci8.0=0x000000ab |
| 1072 | ddr3_tune_rd_dq_wl0_rp_ci2.0=0x81818181,0x81818181,0x84848484,0x84848484 |
| 1073 | ddr3_tune_rd_dqs_ci10.0=0x96969090,0x90909090 |
| 1074 | ddr3_tune_rd_en_ci2.0=0x009c9c9c,0x009a9c98 |
| 1075 | ddr3_tune_wr_dq_wl0_ci12.0=0x93939393,0x93939393,0x93939393,0x93939393 |
| 1076 | ddr3_tune_rd_dq_wl1_rn_ci4.0=0x84848484,0x84848484,0x8c8c8c8c,0x8c8c8c8c |
| 1077 | ddr3_tune_addrc_ci10.0=0x000000af |
| 1078 | ddr3_tune_wr_dq_wl0_ci6.0=0x90909090,0x90909090,0x93939393,0x93939393 |
| 1079 | ddr3_tune_vref_ci12.0=0x0000079e |
| 1080 | ddr3_tune_rd_dq_wl0_rn_ci10.0=0x83838383,0x83838383,0x8c8c8c8c,0x8c8c8c8c |
| 1081 | ddr3_tune_wr_dq_wl1_ci4.0=0x93939393,0x93939393,0x94949494,0x94949494 |
| 1082 | ddr3_tune_wr_dq_ci8.0=0x80808080 |
| 1083 | ddr3_tune_rd_dq_wl1_rp_ci0.0=0x83838383,0x83838383,0x84848484,0x84848484 |
| 1084 | ddr3_tune_wr_dq_wl1_ci10.0=0x95959595,0x95959595,0x95959595,0x95959595 |
| 1085 | ddr3_tune_rd_dq_wl0_rn_ci8.0=0x8a8a8a8a,0x8a8a8a8a,0x89898989,0x89898989 |
| 1086 | ddr3_tune_rd_dq_wl1_rp_ci12.0=0x84848484,0x84848484,0x84848484,0x84848484 |
| 1087 | ddr3_tune_wr_dq_ci10.0=0x80808080 |
| 1088 | ddr3_tune_vref_ci8.0=0x000007df |
| 1089 | ddr3_tune_rd_en_ci12.0=0x009c9c9d,0x00a0a29f |
| 1090 | ddr3_tune_rd_data_dly_ci6.0=0x00000505 |
| 1091 | ddr3_tune_rd_dq_wl0_rp_ci4.0=0x83838383,0x83838383,0x81818181,0x81818181 |
| 1092 | ddr3_tune_rd_dqs_ci12.0=0x91919292,0x92929393 |
| 1093 | ddr3_tune_rd_dqs_ci0.0=0x96969292,0x91919191 |
| 1094 | ddr3_tune_rd_en_ci4.0=0x00979798,0x009c9e9a |
| 1095 | ddr3_tune_rd_data_dly_ci10.0=0x00000505 |
| 1096 | ddr3_tune_addrc_ci0.0=0x000000ad |
| 1097 | ddr3_tune_wr_dq_wl0_ci14.0=0x94949494,0x94949494,0x93939393,0x93939393 |
| 1098 | ddr3_tune_rd_dq_wl1_rn_ci6.0=0x89898989,0x89898989,0x8b8b8b8b,0x8b8b8b8b |
| 1099 | ddr3_tune_addrc_ci12.0=0x000000b3 |
| 1100 | ddr3_tune_wr_dq_wl0_ci8.0=0x93939393,0x93939393,0x93939393,0x93939393 |
| 1101 | ddr3_tune_vref_ci14.0=0x0000079e |
| 1102 | ddr3_tune_rd_dq_wl0_rn_ci12.0=0x83838383,0x83838383,0x83838383,0x83838383 |
| 1103 | ddr3_tune_wr_dq_wl1_ci6.0=0x94949494,0x94949494,0x94949494,0x94949494 |
| 1104 | ddr3_tune_rd_dq_wl1_rp_ci2.0=0x83838383,0x83838383,0x89898989,0x89898989 |
| 1105 | ddr3_tune_wr_dq_wl1_ci12.0=0x94949494,0x94949494,0x94949494,0x94949494 |
| 1106 | ddr3_tune_rd_dq_wl1_rp_ci14.0=0x81818181,0x81818181,0x83838383,0x83838383 |
| 1107 | ddr3_tune_wr_dq_ci12.0=0x80808080 |
| 1108 | ddr3_tune_wr_dq_ci0.0=0x80808080 |
| 1109 | ddr3_tune_rd_en_ci14.0=0x009f9f9f,0x00a2a4a1 |
| 1110 | ddr3_tune_rd_dq_wl0_rn_ci0.0=0x83838383,0x83838383,0x89898989,0x89898989 |
| 1111 | ddr3_tune_rd_data_dly_ci8.0=0x00000505 |
| 1112 | ddr3_tune_rd_dq_wl0_rp_ci6.0=0x80808080,0x80808080,0x8c8c8c8c,0x8c8c8c8c |
| 1113 | ddr3_tune_rd_dqs_ci14.0=0x91919292,0x90909090 |
| 1114 | ddr3_tune_rd_dqs_ci2.0=0x90908f8f,0x95959090 |
| 1115 | ddr3_tune_rd_en_ci6.0=0x009c9d9b,0x009ea09d |
| 1116 | ddr3_tune_rd_data_dly_ci12.0=0x00000505 |
| 1117 | ddr3_tune_vref_ci0.0=0x000007df |
| 1118 | ddr3_tune_addrc_ci2.0=0x000000ae |
| 1119 | ddr3_tune_rd_dq_wl1_rn_ci8.0=0x82828282,0x82828282,0x8b8b8b8b,0x8b8b8b8b |
| 1120 | ddr3_tune_addrc_ci14.0=0x000000b0 |
| 1121 | ddr3_tune_rd_dq_wl1_rn_ci10.0=0x83838383,0x83838383,0x84848484,0x84848484 |
| 1122 | ddr3_tune_rd_dq_wl0_rn_ci14.0=0x83838383,0x83838383,0x83838383,0x83838383 |
| 1123 | ddr3_tune_wr_dq_wl1_ci8.0=0x93939393,0x93939393,0x94949494,0x94949494 |
| 1124 | ddr3_tune_rd_dq_wl1_rp_ci4.0=0x84848484,0x84848484,0x8c8c8c8c,0x8c8c8c8c |
| 1125 | ddr3_tune_wr_dq_wl1_ci14.0=0x95959595,0x95959595,0x95959595,0x95959595 |
| 1126 | ddr3_tune_wr_dq_wl0_ci0.0=0x93939393,0x93939393,0x92929292,0x92929292 |
| 1127 | ddr3_tune_wr_dq_ci14.0=0x80808080 |
| 1128 | ddr3_tune_wr_dq_ci2.0=0x80808080 |
| 1129 | ddr3_tune_rd_dq_wl0_rn_ci2.0=0x81818181,0x81818181,0x84848484,0x84848484 |
| 1130 | ddr3_tune_rd_dq_wl0_rp_ci8.0=0x8a8a8a8a,0x8a8a8a8a,0x89898989,0x89898989 |
| 1131 | ddr3_tune_rd_dqs_ci4.0=0x8f8f9090,0x95959191 |
| 1132 | ddr3_tune_rd_en_ci8.0=0x00a0a0a0,0x009b9e99 |
| 1133 | ddr3_tune_rd_data_dly_ci14.0=0x00000505 |
| 1134 | ddr3_tune_vref_ci2.0=0x000007df |
| 1135 | ddr3_tune_rd_dq_wl0_rp_ci10.0=0x83838383,0x83838383,0x8c8c8c8c,0x8c8c8c8c |
| 1136 | ddr3_tune_rd_data_dly_ci0.0=0x00000505 |
| 1137 | ddr3_tune_addrc_ci4.0=0x000000af |
| 1138 | ddr3_tune_rd_dq_wl1_rn_ci12.0=0x84848484,0x84848484,0x84848484,0x84848484 |
| 1139 | ddr3_tune_rd_dq_wl1_rn_ci0.0=0x83838383,0x83838383,0x84848484,0x84848484 |
| 1140 | ddr3_tune_rd_dq_wl1_rp_ci6.0=0x89898989,0x89898989,0x8b8b8b8b,0x8b8b8b8b |
| 1141 | ddr3_tune_wr_dq_wl0_ci2.0=0x92929292,0x92929292,0x92929292,0x92929292 |
| 1142 | ddr3_tune_wr_dq_wl1_ci0.0=0x92929292,0x92929292,0x92929292,0x92929292 |
| 1143 | ddr3_tune_wr_dq_ci4.0=0x80808080 |
| 1144 | ddr3_tune_rd_dq_wl0_rn_ci4.0=0x83838383,0x83838383,0x81818181,0x81818181 |
| 1145 | ddr3_tune_rd_dqs_ci6.0=0x94948f8f,0x93939393 |
| 1146 | ddr3_tune_vref_ci4.0=0x0000079e |
| 1147 | ddr3_tune_rd_dq_wl0_rp_ci12.0=0x83838383,0x83838383,0x83838383,0x83838383 |
| 1148 | ddr3_tune_rd_data_dly_ci2.0=0x00000404 |
| 1149 | ddr3_tune_addrc_ci6.0=0x000000ab |
| 1150 | ddr3_tune_rd_dq_wl0_rp_ci0.0=0x83838383,0x83838383,0x89898989,0x89898989 |
| 1151 | ddr3_tune_rd_dq_wl1_rn_ci14.0=0x81818181,0x81818181,0x83838383,0x83838383 |
| 1152 | ddr3_tune_rd_en_ci0.0=0x009fa09f,0x00999b98 |
| 1153 | ddr3_tune_wr_dq_wl0_ci10.0=0x94949494,0x94949494,0x96969696,0x96969696 |
| 1154 | ddr3_tune_rd_dq_wl1_rn_ci2.0=0x83838383,0x83838383,0x89898989,0x89898989 |
| 1155 | |
| 1156 | |
| 1157 | # Dram type: Select ONLY ONE of the following DRAM types, to configure all dram related parameteres per type. |
| 1158 | # Dram Type for Arad: |
| 1159 | dram_type_DDR3_HYNIX_H5TQ2G63BFR_TEC_1066=1 |
| 1160 | #dram_type_DDR3_HYNIX_H5TQ2G63BFR_TEC_933=1 |
| 1161 | #dram_type_DDR3_HYNIX_H5TQ2G63BFR_TEC_800=1 |
| 1162 | #dram_type_DDR3_MICRON_MT41J256M16_4GBIT_1066=1 |
| 1163 | #dram_type_DDR3_MICRON_MT41J128M16HA_125_1066=1 |
| 1164 | #dram_type_DDR3_MICRON_MT41J128M16HA_125_933=1 |
| 1165 | #dram_type_DDR3_MICRON_MT41J128M16HA_125_800=1 |
| 1166 | #dram_type_DDR3_MICRON_MT42J64M16LA_15E_667=1 |
| 1167 | #dram_type_DDR3_SAMSUNG_K4B4G1646B_4GBIT_1066=1 |
| 1168 | #dram_type_DDR3_SAMSUNG_K4B1G1646G_933=1 |
| 1169 | #dram_type_DDR3_SAMSUNG_K4B1G1646G_800=1 |
| 1170 | |
| 1171 | ### Setting dram_type_DDR3_HYNIX_H5TQ2G63BFR_TEC_1066 Parameters as Default: |
| 1172 | ## All other dram types parameter resides in arad.soc. choosing another Dram Type will override the following parameters. |
| 1173 | ext_ram_t_rrd=6000 |
| 1174 | ext_ram_columns=1024 |
| 1175 | ext_ram_banks=8 |
| 1176 | ext_ram_ap_bit_pos=10 |
| 1177 | ext_ram_burst_size=32 |
| 1178 | ext_ram_t_ref=3900000 |
| 1179 | ext_ram_t_wr=15000 |
| 1180 | ext_ram_t_wtr=7500 |
| 1181 | ext_ram_t_rtp=7500 |
| 1182 | ext_ram_freq=1066 |
| 1183 | ext_ram_rows=16384 |
| 1184 | ext_ram_jedec=29 |
| 1185 | ext_ram_t_rc=46090 |
| 1186 | ext_ram_t_rcd_rd=13090 |
| 1187 | ext_ram_t_rcd_wr=13090 |
| 1188 | ext_ram_t_rp=13090 |
| 1189 | ext_ram_t_rfc=160000 |
| 1190 | ext_ram_t_ras=33000 |
| 1191 | ext_ram_c_wr_latency=10 |
| 1192 | ext_ram_t_faw=35000 |
| 1193 | ext_ram_c_cas_latency=14 |
| 1194 | ddr3_mem_grade=0x141414 |
| 1195 | |
| 1196 | # DRAM pre-configurations according to config variables which defines |
| 1197 | # Dram Type. supports only DDR3: |
| 1198 | ext_ram_type.BCM88650=DDR3 |
| 1199 | |
| 1200 | # Total Dram Size (MBytes) |
| 1201 | # For 8 drams interfaces, 2 channel each, Each channel 2Gbit Dram. the total DRAM size is 32GBits=4000MBytes. |
| 1202 | ext_ram_total_size.BCM88650=4000 |
| 1203 | |
| 1204 | # Total buffer size allocated for User buffer. Units: Mbytes. Default: '0x0'. |
| 1205 | # Supported suffix: |
| 1206 | # dram - the buffer size will be subtracted from the DRAM size available for packet memory. |
| 1207 | #user_buffer_size=0 |
| 1208 | #user_buffer_size_dram=50 |
| 1209 | |
| 1210 | # DRAM ClamShell (interface swap its HW PIN pairs during init. Note: Only one of DRAMs can have its PIN swapped) |
| 1211 | # Valid values: 0/1 |
| 1212 | #dram0_clamshell_enable.BCM88650=1 |
| 1213 | #dram1_clamshell_enable.BCM88650=1 |
| 1214 | |
| 1215 | # DRAM maximum number of crc error per buffer, buffer deleted by interrupt application. |
| 1216 | #dram_crc_del_buffer_max_reclaims=0 |
| 1217 | |
| 1218 | ### Warmboot ### |
| 1219 | ## Scache initialization for warmboot persistent storage. |
| 1220 | #Save the warm boot data in a file. Allowed values: 3. |
| 1221 | #stable_location.BCM88650=3 |
| 1222 | #Set the warm boot data filename. |
| 1223 | #stable_filename.BCM88650=./warmboot_data |
| 1224 | #Set the warm boot data file size (At least 10MB for PETRA-B, 4MB for ARAD) |
| 1225 | #stable_size.BCM88650=1000000000 |
| 1226 | |
| 1227 | |
| 1228 | ############################## |
| 1229 | # Config variable below are only accessed from dune.soc, and are used to |
| 1230 | # configure BSP / example application / group of formal config variables. |
| 1231 | ############################## |
| 1232 | |
| 1233 | ## If set, always configures synthesizers, even if the configured rate is equal to |
| 1234 | ## their nominal rate. Can be disabled to speedup bringup time (keep in mind that if |
| 1235 | ## disabled, changing a synt to a non-nominal freq and than back to nominal will not |
| 1236 | ## work |
| 1237 | #synt_over.BCM88650=1 |
| 1238 | |
| 1239 | # Local variables for board synthesizers freq. Fabric, combo and nif also configure |
| 1240 | # the *_ref_clock soc properties for these frequencies. core, ddr and phy only |
| 1241 | # configures the synthesizer |
| 1242 | synt_core.BCM88650=100000000 |
| 1243 | synt_ddr.BCM88650=125000000 |
| 1244 | synt_phy.BCM88650=156250000 |
| 1245 | synth_dram_freq.BCM88650=25 |
| 1246 | |
| 1247 | #Configure the reference clock frequencies for NIF and Fabric SerDes |
| 1248 | # Options: 0 - 125MHZ, 1 - 156.25MHz |
| 1249 | serdes_nif_clk_freq.BCM88650=1 |
| 1250 | serdes_fabric_clk_freq.BCM88650=1 |
| 1251 | # IEEE 1588 - |
| 1252 | # configure clock (for 1588 debug, when Broadsync is disabled): |
| 1253 | # DPLL mode/lock: 0 - eci ts pll clk disabled, 1 - configure eci ts pll clk |
| 1254 | # DPLL phase/freq. Default initial: lo = 0x40000000, hi = 0x10000000. |
| 1255 | #phy_1588_dpll_frequency_lock.BCM88650=1 |
| 1256 | #phy_1588_dpll_phase_initial_lo.BCM88650=0x40000000 |
| 1257 | #phy_1588_dpll_phase_initial_hi.BCM88650=0x10000000 |
| 1258 | # port external MAC |
| 1259 | # indication whether external MAC exists or not. |
| 1260 | # 0: 1588 external MAC does not exist |
| 1261 | # 1: 1588 external MAC exists |
| 1262 | # the external MAC substracts the RX time from the correction field |
| 1263 | # and adds the TX time to the correction field. |
| 1264 | #ext_1588_mac_enable_14.BCM88650=1 |
| 1265 | |
| 1266 | ## Trill configurations |
| 1267 | # Trill mode: 0 (disabled) / 1 (coarse-grained) / 2 (fine-grained) |
| 1268 | #trill_mode.BCM88650=1 |
| 1269 | |
| 1270 | # Trill multicast prunning mode: |
| 1271 | # 0: no prunning - vsi is not part of the key |
| 1272 | # 1: VSI prunning: Key is dist-tree,esadit-bit,VSI. |
| 1273 | trill_mc_prune_mode.BCM88650=0 |
| 1274 | |
| 1275 | # Enable SA authentication |
| 1276 | #sa_auth_enabled=1 |
| 1277 | |
| 1278 | # Bridge default logical interfaces allocation IDS |
| 1279 | logical_port_l2_bridge.BCM88650=0 |
| 1280 | logical_port_drop.BCM88650=1 |
| 1281 | |
| 1282 | #logical_port_mim_in.BCM88650=2 |
| 1283 | #logical_port_mim_out.BCM88650=4096 |
| 1284 | |
| 1285 | # Enable EVB application |
| 1286 | #evb_enable=1 |
| 1287 | |
| 1288 | # Enable Flexible QinQ application |
| 1289 | #vlan_translation_match_ipv4=1 |
| 1290 | |
| 1291 | |
| 1292 | # Prepend tag to be 4 bytes or 8 bytes. Default: 4B. |
| 1293 | # Applicable only from ARAD+ |
| 1294 | #prepend_tag_bytes=4B |
| 1295 | |
| 1296 | # The Prepend Tag is located at (12 + 2*offset) bytes from the start of the packet. |
| 1297 | # Range: 0-7. Default: 0 |
| 1298 | #prepend_tag_offset=0 |
| 1299 | |
| 1300 | # Enable ARP (next hop mac extension) feature |
| 1301 | bcm886xx_next_hop_mac_extension_enable.BCM88650=0 |
| 1302 | |
| 1303 | # Set VLAN translate mode. |
| 1304 | # 0: normal |
| 1305 | # 1: advanced mode. Enable vlan edit settings with enhanced user control |
| 1306 | #bcm886xx_vlan_translate_mode=0 |
| 1307 | |
| 1308 | # Set MPLS termination database mode |
| 1309 | # Set MPLS databases location for each MPLS namespace (L1,L2,L3) |
| 1310 | #bcm886xx_mpls_termination_database_mode=0 |
| 1311 | |
| 1312 | # Enable , Disable MPLS indexed. |
| 1313 | # MPLS termination with known label stack location. |
| 1314 | # Must be enabled in case device supports more than 2 MPLS label terminations (L1,L2,L3) |
| 1315 | #mpls_termination_label_index_enable=1 |
| 1316 | |
| 1317 | # Enable FastReRoute labels in device. |
| 1318 | #fast_reroute_labels_enable=0 |
| 1319 | |
| 1320 | # Enable MPLS Context specific. Upstream label assignment in device. |
| 1321 | #mpls_context_specific_label_enable=0 |
| 1322 | |
| 1323 | # MPLS context. |
| 1324 | # Can be global, per port , per interface or per port,interface. |
| 1325 | #mpls_context=global |
| 1326 | |
| 1327 | # MPLS TP MC reserved mac address (01-00-5E-90-00-00). |
| 1328 | # If set device will support My-MAC termination of reserved MC Ethernet |
| 1329 | #mpls_tp_mymac_reserved_address=0 |
| 1330 | |
| 1331 | # MPLS ELI enable disable |
| 1332 | mpls_entropy_label_indicator_enable=0 |
| 1333 | |
| 1334 | |
| 1335 | ######################################### |
| 1336 | ##cfg for BCM88640_A0 - Petra |
| 1337 | ######################################### |
| 1338 | |
| 1339 | force_clk_m_n_divisors_zero_nif0.BCM88640_A0=0 |
| 1340 | force_clk_m_n_divisors_zero_fabric0.BCM88640_A0=1 |
| 1341 | force_clk_m_n_divisors_zero_comb0.BCM88640_A0=0 |
| 1342 | |
| 1343 | combo_ref_clock.BCM88640=312500 |
| 1344 | |
| 1345 | nif_ref_clock.BCM88640_A0=312500 |
| 1346 | |
| 1347 | # Use variable cell size |
| 1348 | system_cell_format.BCM88640_A0=VCS128 |
| 1349 | |
| 1350 | # Core clock speed (MHz) |
| 1351 | core_clock_speed.BCM88640_A0=300 |
| 1352 | |
| 1353 | # Map bcm local port to CPU/NIF interfaces |
| 1354 | ucode_port_0.BCM88640_A0=CPU.0 |
| 1355 | ucode_port_73.BCM88640_A0=CPU.1 |
| 1356 | ucode_port_74.BCM88640_A0=CPU.2 |
| 1357 | ucode_port_75.BCM88640_A0=CPU.3 |
| 1358 | ucode_port_76.BCM88640_A0=CPU.4 |
| 1359 | ucode_port_77.BCM88640_A0=CPU.5 |
| 1360 | ucode_port_78.BCM88640_A0=CPU.6 |
| 1361 | |
| 1362 | # Interlaken ports basic configuration (temporary). |
| 1363 | # This configuration replaces the above XAUI/RXAUI ports config |
| 1364 | # The following PB design constraint is not enforced in SW, so must be taken |
| 1365 | # care of here, when mapping ports to interfaces: |
| 1366 | # If using ilkn0, port 1 (if used) must be mapped to ilkn0 |
| 1367 | # If using ilkn1, port 2 (if used) must be mapped to ilkn1 |
| 1368 | # Note that in our default mapping, port 2 is mapped to RXAUI 6, thus won't |
| 1369 | # work. If one wants to use front panel port 2 with ilkn1, he should be map |
| 1370 | # RAXUI6 to a port != 2. |
| 1371 | #ilkn_num_lanes_0.BCM88640_A0=12 |
| 1372 | #ucode_port_1.BCM88640_A0=ILKN0.0 |
| 1373 | #ucode_port_2.BCM88640_A0=ILKN0.1 |
| 1374 | #ucode_port_3.BCM88640_A0=ILKN0.2 |
| 1375 | #ilkn_num_lanes_1.BCM88640_A0=12 |
| 1376 | #ucode_port_4.BCM88640_A0=RXAUI6 |
| 1377 | #ucode_port_5.BCM88640_A0=ILKN1.0 |
| 1378 | #ucode_port_6.BCM88640_A0=ILKN1.1 |
| 1379 | #ucode_port_7.BCM88640_A0=ILKN1.2 |
| 1380 | |
| 1381 | # Default header type is derived from fap_device_mode: If fap_device_mode is |
| 1382 | # PP, default header type is ETH. Otherwise, defualt header type is TM. |
| 1383 | # Header type per port can be overriden. |
| 1384 | # All options: ETH/RAW/TM/PROG/CPU/STACKING/TDM/TDM_RAW/INJECTED |
| 1385 | |
| 1386 | # Set CPU to work with TM header (ITMH) |
| 1387 | #tm_port_header_type_0.BCM88640_A0=TM |
| 1388 | tm_port_header_type_in_0.BCM88640_A0=TM |
| 1389 | tm_port_header_type_out_0.BCM88640_A0=CPU |
| 1390 | tm_port_header_type_73.BCM88640_A0=TM |
| 1391 | tm_port_header_type_74.BCM88640_A0=TM |
| 1392 | tm_port_header_type_75.BCM88640_A0=TM |
| 1393 | tm_port_header_type_76.BCM88640_A0=TM |
| 1394 | tm_port_header_type_77.BCM88640_A0=TM |
| 1395 | tm_port_header_type_78.BCM88640_A0=TM |
| 1396 | # recycling port |
| 1397 | tm_port_header_type_40.BCM88640_A0=RAW |
| 1398 | ucode_port_40.BCM88640_A0=RCY.0 |
| 1399 | |
| 1400 | # Enable ERP and OLP ports |
| 1401 | num_erp_tm_ports.BCM88640_A0=1 |
| 1402 | num_olp_tm_ports.BCM88640_A0=1 |
| 1403 | num_recycle_tm_ports.BCM88640_A0=1 |
| 1404 | |
| 1405 | # Dram configuration |
| 1406 | # 600 Mhz |
| 1407 | ext_ram_pll_r.BCM88640_A0=4 |
| 1408 | ext_ram_pll_f.BCM88640_A0=47 |
| 1409 | ext_ram_pll_q.BCM88640_A0=1 |
| 1410 | ext_ram_freq.BCM88640_A0=600 |
| 1411 | |
| 1412 | # Dbuff size |
| 1413 | # Allowed values: 256/512/1024/2048. |
| 1414 | ext_ram_dbuff_size.BCM88640_A0=1024 |
| 1415 | |
| 1416 | # Number of external DRAMs. |
| 1417 | # Allowed values for 88x4x: 0/2/3/4/6. |
| 1418 | # Allowed values for 88650: 0/2/3/4/6/8. |
| 1419 | # ext_ram_total_size below assumed this value is 6 for 88x4x and 8 for |
| 1420 | ext_ram_present.BCM88640_A0=6 |
| 1421 | |
| 1422 | # Dram type: Select ONLY ONE of the following DRAM types, to configure all dram |
| 1423 | # related parameteres per type. |
| 1424 | # Dram Type for Pb: |
| 1425 | dram_type_DDR3_MICRON_MT41J64M16_15E.BCM88640_A0=1 |
| 1426 | #dram_type_DDR2_MICRON_K4T51163QE_ZC_LF7.BCM88640_A0=1 |
| 1427 | #dram_type_DDR3_SAMSUNG_K4B1G1646E_HCK0_1333.BCM88640_A0=1 |
| 1428 | #dram_type_DDR3_SAMSUNG_K4B1G1646E_HCK0_1600.BCM88640_A0=1 |
| 1429 | #dram_type_GDDR3_SAMSUNG_K4J52324QE.BCM88640_A0=1 |
| 1430 | #dram_type_DDR3_MICRON_MT41J128M16HA_15E_2G.BCM88640_A0=1 |
| 1431 | |
| 1432 | # QDR configuration |
| 1433 | # Parity. Allowed values: PARITY/ECC. |
| 1434 | ext_qdr_protection_type.BCM88640_A0=PARITY |
| 1435 | ext_qdr_size_mbit.BCM88640_A0=72 |
| 1436 | #QDR type: QDR/QDR2P/QDR3/NONE. |
| 1437 | ext_qdr_type.BCM88640_A0=QDR |
| 1438 | |
| 1439 | # QDR can use the core clock, or using it's own pll. Current example is for 250MHz pll (if used). |
| 1440 | # QDR using own pll configuration |
| 1441 | #ext_qdr_use_core_clock_freq.BCM88640_A0=0 |
| 1442 | #ext_qdr_pll_m.BCM88640_A0=4 |
| 1443 | #ext_qdr_pll_n.BCM88640_A0=4 |
| 1444 | #ext_qdr_pll_p.BCM88640_A0=0 |
| 1445 | |
| 1446 | # QDR using core clock |
| 1447 | ext_qdr_use_core_clock_freq.BCM88640_A0=1 |
| 1448 | |
| 1449 | #Configure MDIO. If parameter is not defined, MDIO is disabled. |
| 1450 | mdio_clock_freq_khz.BCM88640_A0=1000 |
| 1451 | |
| 1452 | # Streaming interface configuration |
| 1453 | streaming_if_enable_timeoutcnt.BCM88640_A0=1 |
| 1454 | streaming_if_timeout_prd.BCM88640_A0=70 |
| 1455 | streaming_if_quiet_mode.BCM88640_A0=0 |
| 1456 | streaming_if_discard_bad_parity.BCM88640_A0=0 |
| 1457 | |
| 1458 | # maximum packet size for WRED tests. 0 - means ignore max packet size. |
| 1459 | discard_mtu_size.BCM88640_A0=0 |
| 1460 | |
| 1461 | # multicast egress vlan membership range. By default: 0-4095. |
| 1462 | egress_multicast_direct_bitmap_min.BCM88640_A0=0 |
| 1463 | egress_multicast_direct_bitmap_max.BCM88640_A0=4095 |
| 1464 | |
| 1465 | # configure flow mapping base to 0 |
| 1466 | flow_mapping_queue_base.BCM88640_A0=0 |
| 1467 | |
| 1468 | dtm_flow_mapping_mode_region_25.BCM88640_A0=0 |
| 1469 | dtm_flow_mapping_mode_region_26.BCM88640_A0=0 |
| 1470 | dtm_flow_mapping_mode_region_27.BCM88640_A0=0 |
| 1471 | dtm_flow_mapping_mode_region_28.BCM88640_A0=0 |
| 1472 | dtm_flow_mapping_mode_region_29.BCM88640_A0=0 |
| 1473 | dtm_flow_mapping_mode_region_30.BCM88640_A0=0 |
| 1474 | dtm_flow_mapping_mode_region_31.BCM88640_A0=0 |
| 1475 | dtm_flow_mapping_mode_region_32.BCM88640_A0=0 |
| 1476 | dtm_flow_mapping_mode_region_33.BCM88640_A0=1 |
| 1477 | dtm_flow_mapping_mode_region_34.BCM88640_A0=1 |
| 1478 | dtm_flow_mapping_mode_region_35.BCM88640_A0=1 |
| 1479 | dtm_flow_mapping_mode_region_36.BCM88640_A0=1 |
| 1480 | dtm_flow_mapping_mode_region_37.BCM88640_A0=1 |
| 1481 | dtm_flow_mapping_mode_region_38.BCM88640_A0=1 |
| 1482 | dtm_flow_mapping_mode_region_39.BCM88640_A0=1 |
| 1483 | dtm_flow_mapping_mode_region_40.BCM88640_A0=1 |
| 1484 | dtm_flow_mapping_mode_region_41.BCM88640_A0=1 |
| 1485 | dtm_flow_mapping_mode_region_42.BCM88640_A0=2 |
| 1486 | dtm_flow_mapping_mode_region_43.BCM88640_A0=2 |
| 1487 | dtm_flow_mapping_mode_region_44.BCM88640_A0=2 |
| 1488 | dtm_flow_mapping_mode_region_45.BCM88640_A0=2 |
| 1489 | dtm_flow_mapping_mode_region_46.BCM88640_A0=2 |
| 1490 | dtm_flow_mapping_mode_region_47.BCM88640_A0=2 |
| 1491 | dtm_flow_mapping_mode_region_48.BCM88640_A0=2 |
| 1492 | dtm_flow_mapping_mode_region_49.BCM88640_A0=2 |
| 1493 | dtm_flow_mapping_mode_region_50.BCM88640_A0=2 |
| 1494 | dtm_flow_mapping_mode_region_51.BCM88640_A0=2 |
| 1495 | dtm_flow_mapping_mode_region_52.BCM88640_A0=2 |
| 1496 | dtm_flow_mapping_mode_region_53.BCM88640_A0=2 |
| 1497 | dtm_flow_mapping_mode_region_54.BCM88640_A0=2 |
| 1498 | dtm_flow_mapping_mode_region_55.BCM88640_A0=2 |
| 1499 | |
| 1500 | # Power up state (DOWN/UP/UP_AND_RELOCK). Can be configured per lane. |
| 1501 | pb_serdes_lane_power_state.BCM88640_A0=UP_AND_RELOCK |
| 1502 | |
| 1503 | # SeDes media type: Pre-configuration for tx params, according to |
| 1504 | # media type. |
| 1505 | # Allowed values: SHORT_BACKPLANE/LONG_BACKPLANE/CHIP2CHIP |
| 1506 | pb_serdes_lane_tx_phys_media_type.BCM88640_A0=SHORT_BACKPLANE |
| 1507 | pb_serdes_lane_tx_phys_media_type_28.BCM88640_A0=CHIP2CHIP |
| 1508 | pb_serdes_lane_tx_phys_media_type_29.BCM88640_A0=CHIP2CHIP |
| 1509 | pb_serdes_lane_tx_phys_media_type_30.BCM88640_A0=CHIP2CHIP |
| 1510 | pb_serdes_lane_tx_phys_media_type_31.BCM88640_A0=CHIP2CHIP |
| 1511 | |
| 1512 | system_is_fe1600_in_system.BCM88640_A0=0 |
| 1513 | |
| 1514 | # Counter engine configuration |
| 1515 | counter_engine_source_1.BCM88640_A0=0 |
| 1516 | counter_engine_statistics_1.BCM88640_A0=4 |
| 1517 | counter_engine_source_2.BCM88640_A0=1 |
| 1518 | counter_engine_statistics_2.BCM88640_A0=4 |
| 1519 | |
| 1520 | # Statistic Reporting |
| 1521 | stat_if_enable=0 |
| 1522 | |
| 1523 | # Clock Phases: 0/90/180/270 |
| 1524 | stat_if_phase=0 |
| 1525 | |
| 1526 | # Rate in nm |
| 1527 | stat_if_sync_rate=0 |
| 1528 | |
| 1529 | # TRUE/FALSE |
| 1530 | stat_if_parity_enable=FALSE |
| 1531 | |
| 1532 | # BILLING/FAP20V |
| 1533 | stat_if_report_mode=BILLING |
| 1534 | |
| 1535 | # Billing Mode |
| 1536 | # EGR_Q_NB/CUD/VSI_VLAN/BOTH_LIFS |
| 1537 | stat_if_report_billing_mode=VSI_VLAN |
| 1538 | |
| 1539 | # Fap20V Mode |
| 1540 | # QUEUE/PACKET |
| 1541 | stat_if_report_fap20v_mode=QUEUE |
| 1542 | |
| 1543 | # QUEUE_NUM/MC_ID (only valid in Fap20V PACKET mode) |
| 1544 | stat_if_report_fap20v_fabric_mc=QUEUE_NUM |
| 1545 | stat_if_report_fap20v_ing_mc=QUEUE_NUM |
| 1546 | |
| 1547 | # TRUE/FALSE (only valid in Fap20V PACKET mode) |
| 1548 | stat_if_report_fap20v_cnm_report=FALSE |
| 1549 | |
| 1550 | # TRUE/FALSE |
| 1551 | stat_if_report_fap20v_count_snoop=FALSE |
| 1552 | stat_if_report_original_pkt_size=FALSE |
| 1553 | stat_if_report_fap20v_single_copy_reported=FALSE |
| 1554 | |
| 1555 | schan_timeout_usec.BCM88640_A0=300000 |
| 1556 | |
| 1557 | |
| 1558 | polled_irq_mode.BCM88640_A0=0 |
| 1559 | polled_irq_delay.BCM88640_A0=1000 |
| 1560 | |
| 1561 | # Set the FTMH Load-Balancing Key extension mode |
| 1562 | # Options for 88650: ENABLED |
| 1563 | # Options for 88640 compatible: DISABLED / 8B_LB_KEY_8B_STACKING_ROUTE_HISTORY / 16B_STACKING_ROUTE_HISTORY |
| 1564 | # Default: DISABLED |
| 1565 | system_ftmh_load_balancing_ext_mode.BCM88640=DISABLED |
| 1566 | |
| 1567 | ######################################### |
| 1568 | ##cfg for BCM88750 |
| 1569 | ######################################### |
| 1570 | |
| 1571 | fabric_device_mode.BCM88750=SINGLE_STAGE_FE2 |
| 1572 | |
| 1573 | is_dual_mode.BCM88750=0 |
| 1574 | system_is_vcs_128_in_system.BCM88750=0 |
| 1575 | |
| 1576 | system_is_dual_mode_in_system.BCM88750=0 |
| 1577 | system_is_single_mode_in_system.BCM88750=1 |
| 1578 | |
| 1579 | system_is_fe600_in_system.BCM88750=0 |
| 1580 | |
| 1581 | system_ref_core_clock_khz.BCM88750=600000 |
| 1582 | |
| 1583 | fabric_merge_cells.BCM88750=0 |
| 1584 | fabric_multicast_mode.BCM88750=DIRECT |
| 1585 | fabric_load_balancing_mode.BCM88750=NORMAL_LOAD_BALANCE |
| 1586 | fabric_tdm_fragment.BCM88750=0x180 |
| 1587 | ##Allows single pipe device to send TDM traffic over the fabric primary pipe - available for Fe1600_B0 only |
| 1588 | #change vcs128_unicast_priority to be lower than 2 - when enabling |
| 1589 | fabric_tdm_over_primary_pipe.BCM88750=0 |
| 1590 | fabric_optimize_partial_links.BCM88750=0 |
| 1591 | vcs128_unicast_priority.BCM88750=2 |
| 1592 | |
| 1593 | polled_irq_mode.BCM88750=0 |
| 1594 | polled_irq_delay.BCM88750=1000 |
| 1595 | |
| 1596 | #Selects if to run MBIST (Memory Built In Self Test) of internal memory (tables) during startup. |
| 1597 | #Supported values: 0=don't run, 1=run, 2=run with extra logs |
| 1598 | #bist_enable.BCM88650=1 |
| 1599 | bist_enable.BCM88750=1 |
| 1600 | #High voltage driver strap. If 0, connected to 1.4V supply; if 1, connected to 1V mode. |
| 1601 | #for specific quad use srd_tx_drv_hv_disable_quad_X where X is (FSRD num * 4 + internal quad) |
| 1602 | srd_tx_drv_hv_disable.BCM88750=0 |
| 1603 | load_firmware.BCM88750=2 |
| 1604 | |
| 1605 | #0-LFEC 1-8b\10b 2-FEC 3-BEC |
| 1606 | backplane_serdes_encoding.BCM88750=2 |
| 1607 | |
| 1608 | #enable\disable CL72 |
| 1609 | port_init_cl72.BCM88750=0 |
| 1610 | #Avaliable speeds for BCM88750: 5750, 6250, 10312, 11500, 12500 |
| 1611 | port_init_speed.BCM88750=10312 |
| 1612 | #LC PLL in\out 0=125MHz 1=156.25MHz |
| 1613 | serdes_fabric_clk_freq_in.BCM88750=1 |
| 1614 | serdes_fabric_clk_freq_out.BCM88750=1 |
| 1615 | serdes_mixed_rate_enable.BCM88750_B0=0 |
| 1616 | |
| 1617 | # VSC128 or VSC256 |
| 1618 | fabric_cell_format.BCM88750=VSC256 |
| 1619 | |
| 1620 | # Core clock speed (MHz) |
| 1621 | core_clock_speed_khz.BCM88750=533333 |
| 1622 | |
| 1623 | ## CMIC interrupts: |
| 1624 | # Enable: Use interrupts completion instead of polling completion for the following operations. |
| 1625 | # Options: 1 - Enable, 0 - Disable. Default: 0. |
| 1626 | # Timeout: delay in Microsecond between the polling, |
| 1627 | # SCHAN: |
| 1628 | schan_intr_enable.BCM88750=0 |
| 1629 | schan_timeout_usec.BCM88750=300000 |
| 1630 | # TDMA |
| 1631 | tdma_intr_enable.BCM88750=0 |
| 1632 | tdma_timeout_usec.BCM88750=80000000 |
| 1633 | # TSLAM |
| 1634 | tslam_intr_enable.BCM88750=0 |
| 1635 | tslam_timeout_usec.BCM88750=80000000 |
| 1636 | # MIIM |
| 1637 | miim_intr_enable.BCM88750=0 |
| 1638 | miim_timeout_usec.BCM88750=300000 |
| 1639 | |
| 1640 | |
| 1641 | ##initialization for warmboot |
| 1642 | stable_location.BCM88750=3 |
| 1643 | stable_size.BCM88750=200000 |
| 1644 | scache_filename.BCM88750=fe1600_warmboot.mem |
| 1645 | |
| 1646 | ############################## |
| 1647 | # Config variable below are only accessed from dune.soc, and are used to |
| 1648 | # configure BSP / example application / group of formal config variables. |
| 1649 | ############################## |
| 1650 | |
| 1651 | # Support (and configure on init) packet processing features. |
| 1652 | # If not defined - only traffic management capabilities are enabled. |
| 1653 | packet_processing=1 |
| 1654 | |
| 1655 | ## PCP (Petra Co-Processor) features |
| 1656 | #pcp_elk.BCM88640_A0=1 |
| 1657 | #pcp_oam.BCM88640_A0=1 |
| 1658 | #pcp_dma.BCM88640_A0=1 |
| 1659 | |
| 1660 | ## Set/Override TDM related config variables |
| 1661 | #tdm.BCM88640_A0=1 |
| 1662 | |
| 1663 | # If set, always configures synthesizers, even if the configured rate is |
| 1664 | # equal to |
| 1665 | # their nominal rate. Can be disabled to speedup bringup time |
| 1666 | # (keep in mind that if disabled, changing a synt to a non-nominal freq and |
| 1667 | # than back to nominal will not work |
| 1668 | #synt_over.BCM88640_A0=1 |
| 1669 | |
| 1670 | # Local variables for board synthesizers freq. Fabric, combo and nif also configure |
| 1671 | # the *_ref_clock soc properties for these frequencies. core, ddr and phy only |
| 1672 | # configures the synthesizer |
| 1673 | synt_core.BCM88640_A0=100000000 |
| 1674 | synt_ddr.BCM88640_A0=125000000 |
| 1675 | synt_phy.BCM88640_A0=156250000 |
| 1676 | |
| 1677 | ## Scache initialization for warmboot persistent storage. |
| 1678 | ## Valid values: 2: Store in dram. 3: Store in a file. |
| 1679 | stable_location=3 |
| 1680 | stable_filename=./warmboot_data |
| 1681 | stable_flags=0 |
| 1682 | stable_size=1000000000 |
| 1683 | |
| 1684 | # Bridge default logical interfaces allocation IDS |
| 1685 | logical_port_l2_bridge.BCM88640=1 |
| 1686 | logical_port_drop.BCM88640=-1 |
| 1687 | |
| 1688 | #logical_port_mim_in.BCM88640=2 |
| 1689 | #logical_port_mim_out.BCM88640=3 |
| 1690 | |
| 1691 | ## IPV6 tunnel |
| 1692 | bcm886xx_ipv6_tunnel_enable=1 |
| 1693 | |
| 1694 | ## Inlif Profile Management Mode - QoS L3 L2 marking mode |
| 1695 | # |
| 1696 | # BCM88660 ONLY |
| 1697 | # |
| 1698 | # QoS L3 L2 marking allows changing the DSCP and/or EXP values |
| 1699 | # of IP and/or MPLS packets according to the incoming port |
| 1700 | # (or inlif), and the Traffic Class/Drop Precedence. |
| 1701 | # |
| 1702 | # The inlif profile is used to control the DSCP/EXP marking. |
| 1703 | # This SOC property controls which mode is used for the inlif profile: |
| 1704 | # 1: Basic mode (1 bit of the inlif profile is reserved and is used for the DSCP/EXP marking). |
| 1705 | # 0: Advanced mode (the user controls which inlif profile values perform DSCP/EXP marking directly). |
| 1706 | #bcm886xx_qos_l3_l2_marking=1 |
| 1707 | |
| 1708 | ## Unicast RPF mode per RIF |
| 1709 | # |
| 1710 | # This SOC property allows the user to set the unicast RPF mode - loose, strict or disabled - per RIF. |
| 1711 | # If disabled, the unicast RPF mode of a RIF is set globally. |
| 1712 | # Options: 0 / 1 |
| 1713 | |
| 1714 | # bcm886xx_l3_ingress_urpf_enable=1 |
| 1715 | |
| 1716 | ## BOS handling mode |
| 1717 | # BCM8866X ONLY |
| 1718 | # |
| 1719 | # There are two ways to handle BOS, controlled by bcm886xx_mpls_termination_mode: |
| 1720 | # 0 - Use BOS as key in lookup. |
| 1721 | # 1 - Don't use it (except for reserved labels). |
| 1722 | # |
| 1723 | #bcm886xx_mpls_termination_key_mode=0 |
| 1724 | |
| 1725 | # Color resolution mode allows the user to have more detailed metering color information. |
| 1726 | # BCM88660 ONLY |
| 1727 | # |
| 1728 | # Options: 0/1 |
| 1729 | # 0: A red result from both Ethernet policer and policer implies DP=3. |
| 1730 | # 1: A red result from the policer implies that DP=2, while a red result from rate (Ethernet policer) implies DP=3. |
| 1731 | #policer_color_resolution_mode=1 |
| 1732 | |
| 1733 | ## Inlif Profile Management Mode - Disable Same Interface Filter |
| 1734 | # BCM8866X ONLY |
| 1735 | # |
| 1736 | # Controls which mode is used for the inlif profile management. |
| 1737 | # 1: Basic mode (1 bit of the inlif profile is reserved and is used for the same-interface filter). |
| 1738 | # 0: Advanced mode (the user controls which inlif profile values have the same-interface filter disabled for them). |
| 1739 | #bcm886xx_logical_interface_bridge_filter_enable=1 |
| 1740 | |
| 1741 | ## Default Block Forwarding Strength |
| 1742 | # |
| 1743 | # Configure the default forwarding strength of blocks. |
| 1744 | # |
| 1745 | # SOC Properties: |
| 1746 | #block_trap_strength_vtt - VTT block forwarding strength |
| 1747 | #block_trap_strength_flp - FLP block forwarding strength |
| 1748 | #block_trap_strength_hash - SLB block forwarding strength (BCM8866X ONLY) |
| 1749 | #block_trap_strength_pmf_0 - PMF 1st lookup forwarding strength |
| 1750 | #block_trap_strength_pmf_1 - PMF 2nd lookup forwarding strength |
| 1751 | # |
| 1752 | # Options: 0-7 |
| 1753 | |
| 1754 | ## Stateful Load Balancing |
| 1755 | # BCM8866X ONLY |
| 1756 | # |
| 1757 | # Stateful Load Balancing (SLB) allows the load balancing of ECMP and LAG |
| 1758 | # groups to become stateful. |
| 1759 | # In standard load balancing, removing a member from the ECMP/LAG |
| 1760 | # group may affect the selected member, since the formula |
| 1761 | # depends on group size. |
| 1762 | # In stateful load balancing the member is selected once and saved. |
| 1763 | # Later, the member is always retrieved, and does not depend on |
| 1764 | # the size of the LAG/ECMP group. |
| 1765 | # |
| 1766 | # resilient_hash_enable - Enable/disable SLB. Values: |
| 1767 | # 1 - Enable SLB. |
| 1768 | # 0 - Disable SLB. |
| 1769 | #resilient_hash_enable=1 |
| 1770 | |
| 1771 | |
| 1772 | #Make Arad SOC properties work for Arad+, by mapping the BCM88660 suffix to BCM88650 |
| 1773 | soc_family.BCM88660=BCM88650 |
| 1774 | #Make Arad SOC properties work for Ardon, by mapping the BCM88202 suffix to BCM88650 |
| 1775 | soc_family.BCM88202=BCM88650 |
| 1776 | |
| 1777 | # Use different mymac addresses for ipv4 and ipv6 when using vrrp for mymac termination. |
| 1778 | #l3_vrrp_ipv6_distinct=1 |
| 1779 | |
| 1780 | # Enable multiple mymac termination mode. In order to enable it, also set |
| 1781 | # l3_vrrp_ipv6_distinct=0 and l3_vrrp_max_vid=0 since vrrp and |
| 1782 | # multiple mymac mode can't co exist. |
| 1783 | #l3_multiple_mymac_termination_enable=1 |
| 1784 | |
| 1785 | # Distinguish between ipv4 and all other l3 protocols when multiple mymac terminating |
| 1786 | #l3_multiple_mymac_termination_mode=1 |
| 1787 | |
| 1788 | # Usually the final DP given by the meter (or the In-DP) is unchanged, and can be from 0-3. |
| 1789 | # When this SOC property is set to 1, when the final INGRESS DP is 2, it is mapped to 1 instead, |
| 1790 | # and thus only the values 0-1 and 3 can be output. |
| 1791 | # This has no effect when policer_color_resolution_mode=1. |
| 1792 | #custom_feature_always_map_result_dp_2_to_1=1 |
| 1793 | |
| 1794 | ############################ |
| 1795 | ### Warmboot & SW State #### |
| 1796 | ############################ |
| 1797 | |
| 1798 | |
| 1799 | ha_hw_journal_size=15728640 |
| 1800 | ha_sw_journal_size=15728640 |
| 1801 | ha_crash_recovery=1 |
| 1802 | |
| 1803 | |
| 1804 | # stable_size - a strict bound on the application's external storage size |
| 1805 | stable_size.BCM88650=281000000 |
| 1806 | stable_size=420000000 |
| 1807 | |
| 1808 | # determine the memory size pre-allocated for the SDK's SW State |
| 1809 | sw_state_max_size.BCM88650=160000000 |
| 1810 | sw_state_max_size=350000000 |
| 1811 | |
| 1812 | # stable location |
| 1813 | ## part of scache initialization for warmboot persistent storage. |
| 1814 | ## values: 1-2:Not Valid for dnx 3: Store in a file 4: Use Shared Mem. |
| 1815 | # 4 is the preffered option, using 3 for Arad and FE in order to regress both modes. |
| 1816 | stable_location.BCM88650=3 |
| 1817 | stable_location.BCM88660=3 |
| 1818 | |
| 1819 | # |
| 1820 | # Enable L3 Source Binds for DPoE SAV |
| 1821 | # |
| 1822 | l3_source_bind_mode=IP |
| 1823 | l3_source_bind_subnet_mode=IP |
| 1824 | ipv4_num_vrfs = 4096 |
| 1825 | |
| 1826 | # |
| 1827 | # Enable ARP checking for L3 Source Binds |
| 1828 | # |
| 1829 | # This feature is not currently used. |
| 1830 | # |
| 1831 | # Valid values for custom_feature_l3_source_bind_arp_relay: |
| 1832 | # 0 - disabled |
| 1833 | # 1 - downstream ARP checking |
| 1834 | # 2 - upstream ARP checking |
| 1835 | # 3 - both downstream and upstream ARP checking |
| 1836 | # |
| 1837 | #custom_feature_l3_source_bind_arp_relay=2 |
| 1838 | |