Shad Ansari | 2f7f9be | 2017-06-07 13:34:53 -0700 | [diff] [blame] | 1 | /* |
| 2 | <:copyright-BRCM:2016:DUAL/GPL:standard |
| 3 | |
| 4 | Broadcom Proprietary and Confidential.(c) 2016 Broadcom |
| 5 | All Rights Reserved |
| 6 | |
| 7 | Unless you and Broadcom execute a separate written software license |
| 8 | agreement governing use of this software, this software is licensed |
| 9 | to you under the terms of the GNU General Public License version 2 |
| 10 | (the "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php, |
| 11 | with the following added to such license: |
| 12 | |
| 13 | As a special exception, the copyright holders of this software give |
| 14 | you permission to link this software with independent modules, and |
| 15 | to copy and distribute the resulting executable under terms of your |
| 16 | choice, provided that you also meet, for each linked independent |
| 17 | module, the terms and conditions of the license of that module. |
| 18 | An independent module is a module which is not derived from this |
| 19 | software. The special exception does not apply to any modifications |
| 20 | of the software. |
| 21 | |
| 22 | Not withstanding the above, under no circumstances may you combine |
| 23 | this software in any way with any other Broadcom software provided |
| 24 | under a license other than the GPL, without Broadcom's express prior |
| 25 | written consent. |
| 26 | |
| 27 | :> |
| 28 | */ |
| 29 | |
| 30 | #ifndef BCMOLT_TR_PCIE_SPECIFIC_H_ |
| 31 | #define BCMOLT_TR_PCIE_SPECIFIC_H_ |
| 32 | |
| 33 | #include "bcmos_system.h" |
| 34 | #include "bcmtr_pcie.h" |
| 35 | |
| 36 | #define DESCRIPTOR_CONTROL 0x00064410 /* Tx Software Descriptor List Control and Status */ |
| 37 | #define WAKEUP_DMA 0x00064414 /* Tx Wake Control */ |
| 38 | #define ERROR_STATUS 0x00064418 /* Tx Engine Error Status */ |
| 39 | |
| 40 | #define INTR2_PCI_STATUS 0x00064318 /* PCI interrupt Status Register */ |
| 41 | |
| 42 | #define DMA_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK 0x00000001 |
| 43 | #define DMA_TX_WAKE_CTRL_WAKE_MASK 0x00000001 |
| 44 | |
| 45 | #define DMA_INTR_STATUS 0x00064318 /* PCI interrupt Status Register */ |
| 46 | #define DMA_INTR_CLEAR 0x00064320 /* PCI interrupt Clear Register */ |
| 47 | #define DMA_INTR_MASK_SET 0x00064328 /* PCI interrupt Mask Set Register */ |
| 48 | #define DMA_INTR_MASK_CLEAR 0x0006432c /* PCI interrupt Mask Clear Register */ |
| 49 | #define DMA_INTR_MASK_STATUS 0x00064324 /* PCI interrupt Mask & Status Register */ |
| 50 | |
| 51 | #define DMA_RX_ERROR_MASK 0x00000008 |
| 52 | #define DMA_RX_DONE_MASK 0x00000004 |
| 53 | #define DMA_TX_DONE_MASK 0x00000001 |
| 54 | #define DMA_TX_ERROR_MASK 0x00000002 |
| 55 | |
| 56 | #define PCIE_L2_INTR_MASK 0x00000020 /* L2 interrupt bit in L1 interrupt status */ |
| 57 | |
| 58 | #define DMA_INTR1_STATUS 0x00069300 /* Interrupt Status Register */ |
| 59 | #define DMA_INTR1_MASK_CLEAR 0x0006930c /* Interrupt Mask Clear Register */ |
| 60 | #define DMA_INTR1_MASK_SET 0x00069308 /* Interrupt Mask Set Register */ |
| 61 | #define DMA_INTA_MASK 0x00000002 |
| 62 | #define DMA_INTA_SHIFT 1 |
| 63 | #define PCIE_STATUS_OFFSET 0x00064068 /* PCIE_PCIE_PCIE_0_PCIE_PCIE_0_MISC_PCIE_STATUS */ |
| 64 | |
| 65 | void bcmtr_connect_isr(void *isr_info); |
| 66 | |
| 67 | /* first parameter is the dest PD, the second parameter is the source field */ |
| 68 | static inline void bcmtr_set_dest_buffer_address(uint32_t *pd, void *value) |
| 69 | { |
| 70 | uint64_t tmp = bcmos_virt_to_phys(value); |
| 71 | |
| 72 | bcm_pci_write32(&pd[PCI_PACKET_LOW_INDEX], (uint32_t)( tmp & 0xffffffffUL)); |
| 73 | bcm_pci_write32(&pd[PCI_PACKET_HIGH_INDEX], (uint32_t)((tmp >> 32) & 0xffffffffUL)); |
| 74 | } |
| 75 | |
| 76 | /* first parameter is the dest PD, the second parameter is the source field */ |
| 77 | static inline void bcmtr_set_source_buffer_address(uint32_t *pd, void *value) |
| 78 | { |
| 79 | uint64_t tmp = bcmos_virt_to_phys(value); |
| 80 | |
| 81 | bcm_pci_write32(&pd[PCI_PACKET_LOW_INDEX], (uint32_t)( tmp & 0xffffffffUL)); |
| 82 | bcm_pci_write32(&pd[PCI_PACKET_HIGH_INDEX], (uint32_t)((tmp >> 32) & 0xffffffffUL)); |
| 83 | } |
| 84 | |
| 85 | static inline bcmos_errno bcmtr_create_tu_rings(uint32_t txlength, uint32_t rxlength, |
| 86 | void **txptr, void **rxptr, |
| 87 | void **txptr_orig, void **rxptr_orig, |
| 88 | unsigned long pcie_reg_base) |
| 89 | { |
| 90 | *txptr = NULL; |
| 91 | *rxptr_orig = NULL; |
| 92 | *txptr = NULL; |
| 93 | *rxptr_orig = NULL; |
| 94 | |
| 95 | return BCM_ERR_OK; |
| 96 | } |
| 97 | static inline void bcmtr_pcie_specific_init(unsigned long pcie_reg_base) {} |
| 98 | static inline void bcmtr_pcie_free_rings(uint32_t device, uint32_t *tx_ptr, uint32_t * rx_ptr){} |
| 99 | static inline void bcmtr_pcie_free_irq(uint32_t irq, void *priv) |
| 100 | { |
| 101 | #ifndef SIMULATION_BUILD |
| 102 | bcmos_int_disconnect((int)irq, priv); |
| 103 | #endif |
| 104 | } |
| 105 | |
| 106 | #define TX_LOCKDEF bcmos_mutex tx_lock; |
| 107 | #define CREATE_TXLOCK(i) bcmos_mutex_create(&bcmtr_pcie_data[i].tx_lock, 0, NULL) |
| 108 | #define DESTROY_TXLOCK(i) bcmos_mutex_destroy(&bcmtr_pcie_data[i].tx_lock) |
| 109 | #define LOCK_TX() bcmos_mutex_lock(¤t_device->tx_lock) |
| 110 | #define UNLOCK_TX() bcmos_mutex_unlock(¤t_device->tx_lock) |
| 111 | |
| 112 | #endif |
| 113 | |